1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip GPIO bank 8 9maintainers: 10 - Heiko Stuebner <heiko@sntech.de> 11 12properties: 13 compatible: 14 enum: 15 - rockchip,gpio-bank 16 - rockchip,rk3188-gpio-bank0 17 18 reg: 19 maxItems: 1 20 21 interrupts: 22 maxItems: 1 23 24 clocks: 25 minItems: 1 26 items: 27 - description: APB interface clock source 28 - description: GPIO debounce reference clock source 29 30 gpio-ranges: true 31 32 gpio-controller: true 33 34 gpio-line-names: true 35 36 "#gpio-cells": 37 const: 2 38 39 interrupt-controller: true 40 41 "#interrupt-cells": 42 const: 2 43 44patternProperties: 45 "^.+-hog(-[0-9]+)?$": 46 type: object 47 48 required: 49 - gpio-hog 50 51required: 52 - compatible 53 - reg 54 - interrupts 55 - clocks 56 - gpio-controller 57 - "#gpio-cells" 58 - interrupt-controller 59 - "#interrupt-cells" 60 61additionalProperties: false 62 63examples: 64 - | 65 #include <dt-bindings/interrupt-controller/arm-gic.h> 66 pinctrl: pinctrl { 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges; 70 71 gpio0: gpio@2000a000 { 72 compatible = "rockchip,rk3188-gpio-bank0"; 73 reg = <0x2000a000 0x100>; 74 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 75 clocks = <&clk_gates8 9>; 76 77 gpio-controller; 78 #gpio-cells = <2>; 79 80 interrupt-controller; 81 #interrupt-cells = <2>; 82 }; 83 84 gpio1: gpio@2003c000 { 85 compatible = "rockchip,gpio-bank"; 86 reg = <0x2003c000 0x100>; 87 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 88 clocks = <&clk_gates8 10>; 89 90 gpio-controller; 91 #gpio-cells = <2>; 92 93 interrupt-controller; 94 #interrupt-cells = <2>; 95 }; 96 }; 97