1*f7176724SAnimesh Agarwal# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*f7176724SAnimesh Agarwal%YAML 1.2 3*f7176724SAnimesh Agarwal--- 4*f7176724SAnimesh Agarwal$id: http://devicetree.org/schemas/gpio/nxp,lpc3220-gpio.yaml# 5*f7176724SAnimesh Agarwal$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f7176724SAnimesh Agarwal 7*f7176724SAnimesh Agarwaltitle: NXP LPC3220 SoC GPIO controller 8*f7176724SAnimesh Agarwal 9*f7176724SAnimesh Agarwalmaintainers: 10*f7176724SAnimesh Agarwal - Animesh Agarwal <animeshagarwal28@gmail.com> 11*f7176724SAnimesh Agarwal 12*f7176724SAnimesh Agarwalproperties: 13*f7176724SAnimesh Agarwal compatible: 14*f7176724SAnimesh Agarwal const: nxp,lpc3220-gpio 15*f7176724SAnimesh Agarwal 16*f7176724SAnimesh Agarwal reg: 17*f7176724SAnimesh Agarwal maxItems: 1 18*f7176724SAnimesh Agarwal 19*f7176724SAnimesh Agarwal gpio-controller: true 20*f7176724SAnimesh Agarwal 21*f7176724SAnimesh Agarwal '#gpio-cells': 22*f7176724SAnimesh Agarwal const: 3 23*f7176724SAnimesh Agarwal description: | 24*f7176724SAnimesh Agarwal 1) bank: 25*f7176724SAnimesh Agarwal 0: GPIO P0 26*f7176724SAnimesh Agarwal 1: GPIO P1 27*f7176724SAnimesh Agarwal 2: GPIO P2 28*f7176724SAnimesh Agarwal 3: GPIO P3 29*f7176724SAnimesh Agarwal 4: GPI P3 30*f7176724SAnimesh Agarwal 5: GPO P3 31*f7176724SAnimesh Agarwal 2) pin number 32*f7176724SAnimesh Agarwal 3) flags: 33*f7176724SAnimesh Agarwal - bit 0 specifies polarity (0 for normal, 1 for inverted) 34*f7176724SAnimesh Agarwal 35*f7176724SAnimesh Agarwalrequired: 36*f7176724SAnimesh Agarwal - compatible 37*f7176724SAnimesh Agarwal - reg 38*f7176724SAnimesh Agarwal - gpio-controller 39*f7176724SAnimesh Agarwal - '#gpio-cells' 40*f7176724SAnimesh Agarwal 41*f7176724SAnimesh AgarwaladditionalProperties: false 42*f7176724SAnimesh Agarwal 43*f7176724SAnimesh Agarwalexamples: 44*f7176724SAnimesh Agarwal - | 45*f7176724SAnimesh Agarwal gpio@40028000 { 46*f7176724SAnimesh Agarwal compatible = "nxp,lpc3220-gpio"; 47*f7176724SAnimesh Agarwal reg = <0x40028000 0x1000>; 48*f7176724SAnimesh Agarwal gpio-controller; 49*f7176724SAnimesh Agarwal #gpio-cells = <3>; /* bank, pin, flags */ 50*f7176724SAnimesh Agarwal }; 51