1*a0e4375cSJim Liu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*a0e4375cSJim Liu%YAML 1.2 3*a0e4375cSJim Liu--- 4*a0e4375cSJim Liu$id: http://devicetree.org/schemas/gpio/nuvoton,sgpio.yaml# 5*a0e4375cSJim Liu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*a0e4375cSJim Liu 7*a0e4375cSJim Liutitle: Nuvoton SGPIO controller 8*a0e4375cSJim Liu 9*a0e4375cSJim Liumaintainers: 10*a0e4375cSJim Liu - Jim LIU <JJLIU0@nuvoton.com> 11*a0e4375cSJim Liu 12*a0e4375cSJim Liudescription: | 13*a0e4375cSJim Liu This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC and detailed 14*a0e4375cSJim Liu information is in the NPCM7XX/8XX SERIAL I/O EXPANSION INTERFACE section. 15*a0e4375cSJim Liu Nuvoton NPCM7xx SGPIO module is combines a serial to parallel IC (HC595) 16*a0e4375cSJim Liu and a parallel to serial IC (HC165). 17*a0e4375cSJim Liu Clock is a division of the APB3 clock. 18*a0e4375cSJim Liu This interface has 4 pins (D_out , D_in, S_CLK, LDSH). 19*a0e4375cSJim Liu NPCM7xx/NPCM8xx have two sgpio modules. Each module can support up 20*a0e4375cSJim Liu to 64 output pins, and up to 64 input pins, the pin is only for GPI or GPO. 21*a0e4375cSJim Liu GPIO pins can be programmed to support the following options 22*a0e4375cSJim Liu - Support interrupt option for each input port and various interrupt 23*a0e4375cSJim Liu sensitivity options (level-high, level-low, edge-high, edge-low) 24*a0e4375cSJim Liu - ngpios is number of nuvoton,input-ngpios GPIO lines and nuvoton,output-ngpios GPIO lines. 25*a0e4375cSJim Liu nuvoton,input-ngpios GPIO lines is only for GPI. 26*a0e4375cSJim Liu nuvoton,output-ngpios GPIO lines is only for GPO. 27*a0e4375cSJim Liu 28*a0e4375cSJim Liuproperties: 29*a0e4375cSJim Liu compatible: 30*a0e4375cSJim Liu enum: 31*a0e4375cSJim Liu - nuvoton,npcm750-sgpio 32*a0e4375cSJim Liu - nuvoton,npcm845-sgpio 33*a0e4375cSJim Liu 34*a0e4375cSJim Liu reg: 35*a0e4375cSJim Liu maxItems: 1 36*a0e4375cSJim Liu 37*a0e4375cSJim Liu gpio-controller: true 38*a0e4375cSJim Liu 39*a0e4375cSJim Liu '#gpio-cells': 40*a0e4375cSJim Liu const: 2 41*a0e4375cSJim Liu 42*a0e4375cSJim Liu interrupts: 43*a0e4375cSJim Liu maxItems: 1 44*a0e4375cSJim Liu 45*a0e4375cSJim Liu clocks: 46*a0e4375cSJim Liu maxItems: 1 47*a0e4375cSJim Liu 48*a0e4375cSJim Liu nuvoton,input-ngpios: 49*a0e4375cSJim Liu $ref: /schemas/types.yaml#/definitions/uint32 50*a0e4375cSJim Liu description: 51*a0e4375cSJim Liu The numbers of GPIO's exposed. GPIO lines are only for GPI. 52*a0e4375cSJim Liu minimum: 0 53*a0e4375cSJim Liu maximum: 64 54*a0e4375cSJim Liu 55*a0e4375cSJim Liu nuvoton,output-ngpios: 56*a0e4375cSJim Liu $ref: /schemas/types.yaml#/definitions/uint32 57*a0e4375cSJim Liu description: 58*a0e4375cSJim Liu The numbers of GPIO's exposed. GPIO lines are only for GPO. 59*a0e4375cSJim Liu minimum: 0 60*a0e4375cSJim Liu maximum: 64 61*a0e4375cSJim Liu 62*a0e4375cSJim Liurequired: 63*a0e4375cSJim Liu - compatible 64*a0e4375cSJim Liu - reg 65*a0e4375cSJim Liu - gpio-controller 66*a0e4375cSJim Liu - '#gpio-cells' 67*a0e4375cSJim Liu - interrupts 68*a0e4375cSJim Liu - nuvoton,input-ngpios 69*a0e4375cSJim Liu - nuvoton,output-ngpios 70*a0e4375cSJim Liu - clocks 71*a0e4375cSJim Liu 72*a0e4375cSJim LiuadditionalProperties: false 73*a0e4375cSJim Liu 74*a0e4375cSJim Liuexamples: 75*a0e4375cSJim Liu - | 76*a0e4375cSJim Liu #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> 77*a0e4375cSJim Liu #include <dt-bindings/interrupt-controller/arm-gic.h> 78*a0e4375cSJim Liu gpio8: gpio@101000 { 79*a0e4375cSJim Liu compatible = "nuvoton,npcm750-sgpio"; 80*a0e4375cSJim Liu reg = <0x101000 0x200>; 81*a0e4375cSJim Liu clocks = <&clk NPCM7XX_CLK_APB3>; 82*a0e4375cSJim Liu interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 83*a0e4375cSJim Liu gpio-controller; 84*a0e4375cSJim Liu #gpio-cells = <2>; 85*a0e4375cSJim Liu nuvoton,input-ngpios = <64>; 86*a0e4375cSJim Liu nuvoton,output-ngpios = <64>; 87*a0e4375cSJim Liu }; 88