xref: /linux/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1*ff2cbd75SLinus Walleij# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*ff2cbd75SLinus Walleij%YAML 1.2
3*ff2cbd75SLinus Walleij---
4*ff2cbd75SLinus Walleij$id: http://devicetree.org/schemas/gpio/intel,ixp4xx-gpio.yaml#
5*ff2cbd75SLinus Walleij$schema: http://devicetree.org/meta-schemas/core.yaml#
6*ff2cbd75SLinus Walleij
7*ff2cbd75SLinus Walleijtitle: Intel IXP4xx XScale Networking Processors GPIO Controller
8*ff2cbd75SLinus Walleij
9*ff2cbd75SLinus Walleijdescription: |
10*ff2cbd75SLinus Walleij  This GPIO controller is found in the Intel IXP4xx
11*ff2cbd75SLinus Walleij  processors. It supports 16 GPIO lines.
12*ff2cbd75SLinus Walleij  The interrupt portions of the GPIO controller is hierarchical.
13*ff2cbd75SLinus Walleij  The synchronous edge detector is part of the GPIO block, but the
14*ff2cbd75SLinus Walleij  actual enabling/disabling of the interrupt line is done in the
15*ff2cbd75SLinus Walleij  main IXP4xx interrupt controller which has a 1-to-1 mapping for
16*ff2cbd75SLinus Walleij  the first 12 GPIO lines to 12 system interrupts.
17*ff2cbd75SLinus Walleij  The remaining 4 GPIO lines can not be used for receiving
18*ff2cbd75SLinus Walleij  interrupts.
19*ff2cbd75SLinus Walleij  The interrupt parent of this GPIO controller must be the
20*ff2cbd75SLinus Walleij  IXP4xx interrupt controller.
21*ff2cbd75SLinus Walleij  GPIO 14 and 15 can be used as clock outputs rather than GPIO,
22*ff2cbd75SLinus Walleij  and this can be enabled by a special flag.
23*ff2cbd75SLinus Walleij
24*ff2cbd75SLinus Walleijmaintainers:
25*ff2cbd75SLinus Walleij  - Linus Walleij <linus.walleij@linaro.org>
26*ff2cbd75SLinus Walleij
27*ff2cbd75SLinus Walleijproperties:
28*ff2cbd75SLinus Walleij  compatible:
29*ff2cbd75SLinus Walleij    const: intel,ixp4xx-gpio
30*ff2cbd75SLinus Walleij
31*ff2cbd75SLinus Walleij  reg:
32*ff2cbd75SLinus Walleij    maxItems: 1
33*ff2cbd75SLinus Walleij
34*ff2cbd75SLinus Walleij  gpio-controller: true
35*ff2cbd75SLinus Walleij
36*ff2cbd75SLinus Walleij  "#gpio-cells":
37*ff2cbd75SLinus Walleij    const: 2
38*ff2cbd75SLinus Walleij
39*ff2cbd75SLinus Walleij  interrupt-controller: true
40*ff2cbd75SLinus Walleij
41*ff2cbd75SLinus Walleij  "#interrupt-cells":
42*ff2cbd75SLinus Walleij    const: 2
43*ff2cbd75SLinus Walleij
44*ff2cbd75SLinus Walleij  intel,ixp4xx-gpio14-clkout:
45*ff2cbd75SLinus Walleij    description: If defined, enables clock output on GPIO 14
46*ff2cbd75SLinus Walleij      instead of GPIO.
47*ff2cbd75SLinus Walleij    type: boolean
48*ff2cbd75SLinus Walleij
49*ff2cbd75SLinus Walleij  intel,ixp4xx-gpio15-clkout:
50*ff2cbd75SLinus Walleij    description: If defined, enables clock output on GPIO 15
51*ff2cbd75SLinus Walleij      instead of GPIO.
52*ff2cbd75SLinus Walleij    type: boolean
53*ff2cbd75SLinus Walleij
54*ff2cbd75SLinus Walleijrequired:
55*ff2cbd75SLinus Walleij  - compatible
56*ff2cbd75SLinus Walleij  - reg
57*ff2cbd75SLinus Walleij  - "#gpio-cells"
58*ff2cbd75SLinus Walleij  - interrupt-controller
59*ff2cbd75SLinus Walleij  - "#interrupt-cells"
60*ff2cbd75SLinus Walleij
61*ff2cbd75SLinus WalleijadditionalProperties: false
62*ff2cbd75SLinus Walleij
63*ff2cbd75SLinus Walleijexamples:
64*ff2cbd75SLinus Walleij  - |
65*ff2cbd75SLinus Walleij    #include <dt-bindings/interrupt-controller/irq.h>
66*ff2cbd75SLinus Walleij    gpio@c8004000 {
67*ff2cbd75SLinus Walleij        compatible = "intel,ixp4xx-gpio";
68*ff2cbd75SLinus Walleij        reg = <0xc8004000 0x1000>;
69*ff2cbd75SLinus Walleij        gpio-controller;
70*ff2cbd75SLinus Walleij        #gpio-cells = <2>;
71*ff2cbd75SLinus Walleij        interrupt-controller;
72*ff2cbd75SLinus Walleij        #interrupt-cells = <2>;
73*ff2cbd75SLinus Walleij    };
74