1*95e7fc84SWeilong Chen# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*95e7fc84SWeilong Chen%YAML 1.2 3*95e7fc84SWeilong Chen--- 4*95e7fc84SWeilong Chen$id: http://devicetree.org/schemas/gpio/hisilicon,ascend910-gpio.yaml# 5*95e7fc84SWeilong Chen$schema: http://devicetree.org/meta-schemas/core.yaml# 6*95e7fc84SWeilong Chen 7*95e7fc84SWeilong Chentitle: HiSilicon common GPIO controller 8*95e7fc84SWeilong Chen 9*95e7fc84SWeilong Chenmaintainers: 10*95e7fc84SWeilong Chen - Jay Fang <f.fangjian@huawei.com> 11*95e7fc84SWeilong Chen 12*95e7fc84SWeilong Chendescription: 13*95e7fc84SWeilong Chen The HiSilicon common GPIO controller can be used for many different 14*95e7fc84SWeilong Chen types of SoC such as Huawei Ascend AI series chips. 15*95e7fc84SWeilong Chen 16*95e7fc84SWeilong Chenproperties: 17*95e7fc84SWeilong Chen compatible: 18*95e7fc84SWeilong Chen const: hisilicon,ascend910-gpio 19*95e7fc84SWeilong Chen 20*95e7fc84SWeilong Chen reg: 21*95e7fc84SWeilong Chen maxItems: 1 22*95e7fc84SWeilong Chen 23*95e7fc84SWeilong Chen interrupts: 24*95e7fc84SWeilong Chen maxItems: 1 25*95e7fc84SWeilong Chen 26*95e7fc84SWeilong Chen gpio-controller: true 27*95e7fc84SWeilong Chen 28*95e7fc84SWeilong Chen "#gpio-cells": 29*95e7fc84SWeilong Chen const: 2 30*95e7fc84SWeilong Chen 31*95e7fc84SWeilong Chen ngpios: 32*95e7fc84SWeilong Chen minimum: 1 33*95e7fc84SWeilong Chen maximum: 32 34*95e7fc84SWeilong Chen 35*95e7fc84SWeilong Chenrequired: 36*95e7fc84SWeilong Chen - compatible 37*95e7fc84SWeilong Chen - reg 38*95e7fc84SWeilong Chen - interrupts 39*95e7fc84SWeilong Chen - gpio-controller 40*95e7fc84SWeilong Chen - "#gpio-cells" 41*95e7fc84SWeilong Chen - ngpios 42*95e7fc84SWeilong Chen 43*95e7fc84SWeilong ChenadditionalProperties: false 44*95e7fc84SWeilong Chen 45*95e7fc84SWeilong Chenexamples: 46*95e7fc84SWeilong Chen - | 47*95e7fc84SWeilong Chen #include <dt-bindings/interrupt-controller/arm-gic.h> 48*95e7fc84SWeilong Chen 49*95e7fc84SWeilong Chen gpio@840d0000 { 50*95e7fc84SWeilong Chen compatible = "hisilicon,ascend910-gpio"; 51*95e7fc84SWeilong Chen reg = <0x840d0000 0x1000>; 52*95e7fc84SWeilong Chen ngpios = <32>; 53*95e7fc84SWeilong Chen gpio-controller; 54*95e7fc84SWeilong Chen #gpio-cells = <2>; 55*95e7fc84SWeilong Chen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 56*95e7fc84SWeilong Chen }; 57