xref: /linux/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml (revision 594ce0b8a998aa4d05827cd7c0d0dcec9a1e3ae2) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Marvell EBU GPIO controller
8
9maintainers:
10  - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11  - Andrew Lunn <andrew@lunn.ch>
12
13properties:
14  compatible:
15    oneOf:
16      - enum:
17          - marvell,armada-8k-gpio
18          - marvell,orion-gpio
19
20      - items:
21          - enum:
22              - marvell,mv78200-gpio
23              - marvell,armada-370-gpio
24          - const: marvell,orion-gpio
25
26      - description: Deprecated binding
27        items:
28          - const: marvell,armadaxp-gpio
29          - const: marvell,orion-gpio
30        deprecated: true
31
32  reg:
33    description: |
34      Address and length of the register set for the device. Not used for
35      marvell,armada-8k-gpio.
36
37      A second entry can be provided, for the PWM function using the GPIO Blink
38      Counter on/off registers.
39    minItems: 1
40    maxItems: 2
41
42  reg-names:
43    items:
44      - const: gpio
45      - const: pwm
46    minItems: 1
47
48  offset:
49    $ref: /schemas/types.yaml#/definitions/uint32
50    description: Offset in the register map for the gpio registers (in bytes)
51
52  interrupts:
53    description: |
54      The list of interrupts that are used for all the pins managed by this
55      GPIO bank. There can be more than one interrupt (example: 1 interrupt
56      per 8 pins on Armada XP, which means 4 interrupts per bank of 32
57      GPIOs).
58    minItems: 1
59    maxItems: 4
60
61  interrupt-controller: true
62
63  "#interrupt-cells":
64    const: 2
65
66  gpio-controller: true
67
68  ngpios:
69    minimum: 1
70    maximum: 32
71
72  "#gpio-cells":
73    const: 2
74
75  marvell,pwm-offset:
76    $ref: /schemas/types.yaml#/definitions/uint32
77    description: Offset in the register map for the pwm registers (in bytes)
78
79  "#pwm-cells":
80    description:
81      The first cell is the GPIO line number. The second cell is the period
82      in nanoseconds.
83    const: 2
84
85  clocks:
86    description:
87      Clock(s) used for PWM function.
88    items:
89      - description: Core clock
90      - description: AXI bus clock
91    minItems: 1
92
93  clock-names:
94    items:
95      - const: core
96      - const: axi
97    minItems: 1
98
99required:
100  - compatible
101  - gpio-controller
102  - ngpios
103  - "#gpio-cells"
104
105allOf:
106  - if:
107      properties:
108        compatible:
109          contains:
110            const: marvell,armada-8k-gpio
111    then:
112      required:
113        - offset
114    else:
115      required:
116        - reg
117
118unevaluatedProperties: false
119
120examples:
121  - |
122    gpio@d0018100 {
123      compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
124      reg = <0xd0018100 0x40>, <0xd0018800 0x30>;
125      ngpios = <32>;
126      gpio-controller;
127      #gpio-cells = <2>;
128      interrupt-controller;
129      #interrupt-cells = <2>;
130      interrupts = <16>, <17>, <18>, <19>;
131    };
132
133  - |
134    gpio@18140 {
135      compatible = "marvell,armada-370-gpio", "marvell,orion-gpio";
136      reg = <0x18140 0x40>, <0x181c8 0x08>;
137      reg-names = "gpio", "pwm";
138      ngpios = <17>;
139      gpio-controller;
140      #gpio-cells = <2>;
141      #pwm-cells = <2>;
142      interrupt-controller;
143      #interrupt-cells = <2>;
144      interrupts = <87>, <88>, <89>;
145      clocks = <&coreclk 0>;
146    };
147