1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic MMIO GPIO 8 9maintainers: 10 - Linus Walleij <linus.walleij@linaro.org> 11 - Bartosz Golaszewski <brgl@bgdev.pl> 12 13description: 14 Some simple GPIO controllers may consist of a single data register or a pair 15 of set/clear-bit registers. Such controllers are common for glue logic in 16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped 17 NAND-style parallel busses. 18 19properties: 20 compatible: 21 enum: 22 - brcm,bcm6345-gpio 23 - ni,169445-nand-gpio 24 - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller 25 26 big-endian: true 27 28 '#gpio-cells': 29 const: 2 30 31 gpio-controller: true 32 33 little-endian: true 34 35 reg: 36 minItems: 1 37 description: 38 A list of registers in the controller. The width of each register is 39 determined by its size. All registers must have the same width. The number 40 of GPIOs is set by the width, with bit 0 corresponding to GPIO 0, unless 41 the ngpios property further restricts the number of used lines. 42 items: 43 - description: 44 Register to READ the value of the GPIO lines. If GPIO line is high, 45 the bit will be set. If the GPIO line is low, the bit will be cleared. 46 This register may also be used to drive GPIOs if the SET register is 47 omitted. 48 - description: 49 Register to SET the value of the GPIO lines. Setting a bit in this 50 register will drive the GPIO line high. 51 - description: 52 Register to CLEAR the value of the GPIO lines. Setting a bit in this 53 register will drive the GPIO line low. If this register is omitted, 54 the SET register will be used to clear the GPIO lines as well, by 55 actively writing the line with 0. 56 - description: 57 Register to set the line as OUTPUT. Setting a bit in this register 58 will turn that line into an output line. Conversely, clearing a bit 59 will turn that line into an input. 60 - description: 61 Register to set this line as INPUT. Setting a bit in this register 62 will turn that line into an input line. Conversely, clearing a bit 63 will turn that line into an output. 64 65 reg-names: 66 minItems: 1 67 maxItems: 5 68 items: 69 enum: 70 - dat 71 - set 72 - clr 73 - dirout 74 - dirin 75 76 native-endian: true 77 78 ngpios: 79 minimum: 1 80 maximum: 63 81 description: 82 If this property is present the number of usable GPIO lines are restricted 83 to the first 0 .. ngpios lines. This is useful when the GPIO MMIO register 84 has 32 bits for GPIO but only the first 12 are actually connected to 85 real electronics, and then we set ngpios to 12. 86 87 no-output: 88 $ref: /schemas/types.yaml#/definitions/flag 89 description: 90 If this property is present, the controller cannot drive the GPIO lines. 91 92required: 93 - compatible 94 - reg 95 - reg-names 96 - '#gpio-cells' 97 - gpio-controller 98 99additionalProperties: false 100 101examples: 102 - | 103 gpio@1f300010 { 104 compatible = "ni,169445-nand-gpio"; 105 reg = <0x1f300010 0x4>; 106 reg-names = "dat"; 107 gpio-controller; 108 #gpio-cells = <2>; 109 }; 110 111 gpio@e0100000 { 112 compatible = "wd,mbl-gpio"; 113 reg-names = "dat"; 114 reg = <0xe0100000 0x1>; 115 #gpio-cells = <2>; 116 gpio-controller; 117 no-output; 118 }; 119 120 gpio@fffe0406 { 121 compatible = "brcm,bcm6345-gpio"; 122 reg-names = "dirout", "dat"; 123 reg = <0xfffe0406 2>, <0xfffe040a 2>; 124 ngpios = <15>; 125 native-endian; 126 gpio-controller; 127 #gpio-cells = <2>; 128 }; 129