1*672d644aSRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*672d644aSRob Herring (Arm)%YAML 1.2 3*672d644aSRob Herring (Arm)--- 4*672d644aSRob Herring (Arm)$id: http://devicetree.org/schemas/apm,xgene-gpio-sb.yaml# 5*672d644aSRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml# 6*672d644aSRob Herring (Arm) 7*672d644aSRob Herring (Arm)title: APM X-Gene Standby GPIO controller 8*672d644aSRob Herring (Arm) 9*672d644aSRob Herring (Arm)maintainers: 10*672d644aSRob Herring (Arm) - Khuong Dinh <khuong@os.amperecomputing.com> 11*672d644aSRob Herring (Arm) 12*672d644aSRob Herring (Arm)description: | 13*672d644aSRob Herring (Arm) This is a gpio controller in the standby domain. It also supports interrupt in 14*672d644aSRob Herring (Arm) some particular pins which are sourced to its parent interrupt controller 15*672d644aSRob Herring (Arm) as diagram below: 16*672d644aSRob Herring (Arm) +-----------------+ 17*672d644aSRob Herring (Arm) | X-Gene standby | 18*672d644aSRob Herring (Arm) | GPIO controller +------ GPIO_0 19*672d644aSRob Herring (Arm) +------------+ | | ... 20*672d644aSRob Herring (Arm) | Parent IRQ | EXT_INT_0 | +------ GPIO_8/EXT_INT_0 21*672d644aSRob Herring (Arm) | controller | (SPI40) | | ... 22*672d644aSRob Herring (Arm) | (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N 23*672d644aSRob Herring (Arm) | | ... | | 24*672d644aSRob Herring (Arm) | | EXT_INT_N | +------ GPIO_[N+9] 25*672d644aSRob Herring (Arm) | | (SPI[40 + N])| | ... 26*672d644aSRob Herring (Arm) | +--------------+ +------ GPIO_MAX 27*672d644aSRob Herring (Arm) +------------+ +-----------------+ 28*672d644aSRob Herring (Arm) 29*672d644aSRob Herring (Arm)properties: 30*672d644aSRob Herring (Arm) compatible: 31*672d644aSRob Herring (Arm) const: apm,xgene-gpio-sb 32*672d644aSRob Herring (Arm) 33*672d644aSRob Herring (Arm) reg: 34*672d644aSRob Herring (Arm) maxItems: 1 35*672d644aSRob Herring (Arm) 36*672d644aSRob Herring (Arm) '#gpio-cells': 37*672d644aSRob Herring (Arm) const: 2 38*672d644aSRob Herring (Arm) 39*672d644aSRob Herring (Arm) gpio-controller: true 40*672d644aSRob Herring (Arm) 41*672d644aSRob Herring (Arm) interrupts: 42*672d644aSRob Herring (Arm) description: 43*672d644aSRob Herring (Arm) List of interrupt specifiers for EXT_INT_0 through EXT_INT_N. The first 44*672d644aSRob Herring (Arm) entry must correspond to EXT_INT_0. 45*672d644aSRob Herring (Arm) 46*672d644aSRob Herring (Arm) '#interrupt-cells': 47*672d644aSRob Herring (Arm) const: 2 48*672d644aSRob Herring (Arm) description: 49*672d644aSRob Herring (Arm) First cell selects EXT_INT_N (0-N), second cell specifies flags 50*672d644aSRob Herring (Arm) 51*672d644aSRob Herring (Arm) interrupt-controller: true 52*672d644aSRob Herring (Arm) 53*672d644aSRob Herring (Arm) apm,nr-gpios: 54*672d644aSRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 55*672d644aSRob Herring (Arm) description: Number of GPIO pins 56*672d644aSRob Herring (Arm) 57*672d644aSRob Herring (Arm) apm,nr-irqs: 58*672d644aSRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 59*672d644aSRob Herring (Arm) description: Number of interrupt pins 60*672d644aSRob Herring (Arm) 61*672d644aSRob Herring (Arm) apm,irq-start: 62*672d644aSRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 63*672d644aSRob Herring (Arm) description: Lowest GPIO pin supporting interrupts 64*672d644aSRob Herring (Arm) 65*672d644aSRob Herring (Arm)required: 66*672d644aSRob Herring (Arm) - compatible 67*672d644aSRob Herring (Arm) - reg 68*672d644aSRob Herring (Arm) - '#gpio-cells' 69*672d644aSRob Herring (Arm) - gpio-controller 70*672d644aSRob Herring (Arm) - interrupts 71*672d644aSRob Herring (Arm) - '#interrupt-cells' 72*672d644aSRob Herring (Arm) - interrupt-controller 73*672d644aSRob Herring (Arm) 74*672d644aSRob Herring (Arm)additionalProperties: false 75*672d644aSRob Herring (Arm) 76*672d644aSRob Herring (Arm)examples: 77*672d644aSRob Herring (Arm) - | 78*672d644aSRob Herring (Arm) gpio@17001000 { 79*672d644aSRob Herring (Arm) compatible = "apm,xgene-gpio-sb"; 80*672d644aSRob Herring (Arm) reg = <0x17001000 0x400>; 81*672d644aSRob Herring (Arm) #gpio-cells = <2>; 82*672d644aSRob Herring (Arm) gpio-controller; 83*672d644aSRob Herring (Arm) interrupts = <0x0 0x28 0x1>, 84*672d644aSRob Herring (Arm) <0x0 0x29 0x1>, 85*672d644aSRob Herring (Arm) <0x0 0x2a 0x1>, 86*672d644aSRob Herring (Arm) <0x0 0x2b 0x1>, 87*672d644aSRob Herring (Arm) <0x0 0x2c 0x1>, 88*672d644aSRob Herring (Arm) <0x0 0x2d 0x1>; 89*672d644aSRob Herring (Arm) #interrupt-cells = <2>; 90*672d644aSRob Herring (Arm) interrupt-controller; 91*672d644aSRob Herring (Arm) apm,nr-gpios = <22>; 92*672d644aSRob Herring (Arm) apm,nr-irqs = <6>; 93*672d644aSRob Herring (Arm) apm,irq-start = <8>; 94*672d644aSRob Herring (Arm) }; 95