1*1adcbea4SAlan TullAltera SOCFPGA Arria10 FPGA Manager 2*1adcbea4SAlan Tull 3*1adcbea4SAlan TullRequired properties: 4*1adcbea4SAlan Tull- compatible : should contain "altr,socfpga-a10-fpga-mgr" 5*1adcbea4SAlan Tull- reg : base address and size for memory mapped io. 6*1adcbea4SAlan Tull - The first index is for FPGA manager register access. 7*1adcbea4SAlan Tull - The second index is for writing FPGA configuration data. 8*1adcbea4SAlan Tull- resets : Phandle and reset specifier for the device's reset. 9*1adcbea4SAlan Tull- clocks : Clocks used by the device. 10*1adcbea4SAlan Tull 11*1adcbea4SAlan TullExample: 12*1adcbea4SAlan Tull 13*1adcbea4SAlan Tull fpga_mgr: fpga-mgr@ffd03000 { 14*1adcbea4SAlan Tull compatible = "altr,socfpga-a10-fpga-mgr"; 15*1adcbea4SAlan Tull reg = <0xffd03000 0x100 16*1adcbea4SAlan Tull 0xffcfe400 0x20>; 17*1adcbea4SAlan Tull clocks = <&l4_mp_clk>; 18*1adcbea4SAlan Tull resets = <&rst FPGAMGR_RESET>; 19*1adcbea4SAlan Tull }; 20