xref: /linux/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml (revision eed4edda910fe34dfae8c6bfbcf57f4593a54295) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx firmware driver
8
9maintainers:
10  - Nava kishore Manne <nava.kishore.manne@amd.com>
11
12description: The zynqmp-firmware node describes the interface to platform
13  firmware. ZynqMP has an interface to communicate with secure firmware.
14  Firmware driver provides an interface to firmware APIs. Interface APIs
15  can be used by any driver to communicate to PMUFW(Platform Management Unit).
16  These requests include clock management, pin control, device control,
17  power management service, FPGA service and other platform management
18  services.
19
20properties:
21  compatible:
22    oneOf:
23      - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24        const: xlnx,zynqmp-firmware
25
26      - description: For implementations complying for Versal.
27        const: xlnx,versal-firmware
28
29  method:
30    description: |
31                 The method of calling the PM-API firmware layer.
32                 Permitted values are.
33                 - "smc" : SMC #0, following the SMCCC
34                 - "hvc" : HVC #0, following the SMCCC
35
36    $ref: /schemas/types.yaml#/definitions/string-array
37    enum:
38      - smc
39      - hvc
40
41  "#power-domain-cells":
42    const: 1
43
44  versal_fpga:
45    $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
46    description: Compatible of the FPGA device.
47    type: object
48
49  zynqmp-aes:
50    $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
51    description: The ZynqMP AES-GCM hardened cryptographic accelerator is
52      used to encrypt or decrypt the data with provided key and initialization
53      vector.
54    type: object
55
56  clock-controller:
57    $ref: /schemas/clock/xlnx,versal-clk.yaml#
58    description: The clock controller is a hardware block of Xilinx versal
59      clock tree. It reads required input clock frequencies from the devicetree
60      and acts as clock provider for all clock consumers of PS clocks.list of
61      clock specifiers which are external input clocks to the given clock
62      controller.
63    type: object
64
65required:
66  - compatible
67
68additionalProperties: false
69
70examples:
71  - |
72    #include <dt-bindings/power/xlnx-zynqmp-power.h>
73    firmware {
74      zynqmp_firmware: zynqmp-firmware {
75        #power-domain-cells = <1>;
76        };
77    };
78
79    sata {
80      power-domains = <&zynqmp_firmware PD_SATA>;
81    };
82
83    versal-firmware {
84      compatible = "xlnx,versal-firmware";
85      method = "smc";
86
87      versal_fpga: versal_fpga {
88        compatible = "xlnx,versal-fpga";
89      };
90
91      xlnx_aes: zynqmp-aes {
92        compatible = "xlnx,zynqmp-aes";
93      };
94
95      versal_clk: clock-controller {
96        #clock-cells = <1>;
97        compatible = "xlnx,versal-clk";
98        clocks = <&ref>, <&pl_alt_ref>;
99        clock-names = "ref", "pl_alt_ref";
100      };
101    };
102
103...
104