xref: /linux/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml (revision d5859510d35d8e7d63fed5169f1775317f40fb03) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx firmware driver
8
9maintainers:
10  - Nava kishore Manne <nava.kishore.manne@amd.com>
11
12description: The zynqmp-firmware node describes the interface to platform
13  firmware. ZynqMP has an interface to communicate with secure firmware.
14  Firmware driver provides an interface to firmware APIs. Interface APIs
15  can be used by any driver to communicate to PMUFW(Platform Management Unit).
16  These requests include clock management, pin control, device control,
17  power management service, FPGA service and other platform management
18  services.
19
20properties:
21  compatible:
22    oneOf:
23      - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24        const: xlnx,zynqmp-firmware
25
26      - description: For implementations complying for Versal.
27        const: xlnx,versal-firmware
28
29      - description: For implementations complying for Versal NET.
30        items:
31          - enum:
32              - xlnx,versal-net-firmware
33          - const: xlnx,versal-firmware
34
35  method:
36    description: |
37                 The method of calling the PM-API firmware layer.
38                 Permitted values are.
39                 - "smc" : SMC #0, following the SMCCC
40                 - "hvc" : HVC #0, following the SMCCC
41
42    $ref: /schemas/types.yaml#/definitions/string-array
43    enum:
44      - smc
45      - hvc
46
47  "#power-domain-cells":
48    const: 1
49
50  clock-controller:
51    $ref: /schemas/clock/xlnx,versal-clk.yaml#
52    description: The clock controller is a hardware block of Xilinx versal
53      clock tree. It reads required input clock frequencies from the devicetree
54      and acts as clock provider for all clock consumers of PS clocks.list of
55      clock specifiers which are external input clocks to the given clock
56      controller.
57    type: object
58
59  gpio:
60    $ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
61    description: The gpio node describes connect to PS_MODE pins via firmware
62      interface.
63    type: object
64
65  soc-nvmem:
66    $ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
67    description: The ZynqMP MPSoC provides access to the hardware related data
68      like SOC revision, IDCODE and specific purpose efuses.
69    type: object
70
71  pcap:
72    $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml
73    description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
74      configure the Programmable Logic (PL). The configuration uses the
75      firmware interface.
76    type: object
77
78  pinctrl:
79    $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
80    description: The pinctrl node provides access to pinconfig and pincontrol
81      functionality available in firmware.
82    type: object
83
84  power-management:
85    $ref: /schemas/power/reset/xlnx,zynqmp-power.yaml#
86    description: The zynqmp-power node describes the power management
87      configurations. It will control remote suspend/shutdown interfaces.
88    type: object
89
90  reset-controller:
91    $ref: /schemas/reset/xlnx,zynqmp-reset.yaml#
92    description: The reset-controller node describes connection to the reset
93      functionality via firmware interface.
94    type: object
95
96  versal-fpga:
97    $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
98    description: Compatible of the FPGA device.
99    type: object
100
101  zynqmp-aes:
102    $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
103    description: The ZynqMP AES-GCM hardened cryptographic accelerator is
104      used to encrypt or decrypt the data with provided key and initialization
105      vector.
106    type: object
107
108required:
109  - compatible
110
111additionalProperties: false
112
113examples:
114  - |
115    #include <dt-bindings/power/xlnx-zynqmp-power.h>
116    firmware {
117      zynqmp_firmware: zynqmp-firmware {
118        #power-domain-cells = <1>;
119        soc-nvmem {
120          compatible = "xlnx,zynqmp-nvmem-fw";
121          nvmem-layout {
122            compatible = "fixed-layout";
123            #address-cells = <1>;
124            #size-cells = <1>;
125
126            soc_revision: soc-revision@0 {
127                reg = <0x0 0x4>;
128            };
129          };
130        };
131        gpio {
132          compatible = "xlnx,zynqmp-gpio-modepin";
133          gpio-controller;
134          #gpio-cells = <2>;
135        };
136        pcap {
137          compatible = "xlnx,zynqmp-pcap-fpga";
138        };
139        pinctrl {
140          compatible = "xlnx,zynqmp-pinctrl";
141        };
142        power-management {
143          compatible = "xlnx,zynqmp-power";
144          interrupts = <0 35 4>;
145        };
146        reset-controller {
147          compatible = "xlnx,zynqmp-reset";
148          #reset-cells = <1>;
149        };
150      };
151    };
152
153    sata {
154      power-domains = <&zynqmp_firmware PD_SATA>;
155    };
156
157    versal-firmware {
158      compatible = "xlnx,versal-firmware";
159      method = "smc";
160
161      versal_fpga: versal-fpga {
162        compatible = "xlnx,versal-fpga";
163      };
164
165      xlnx_aes: zynqmp-aes {
166        compatible = "xlnx,zynqmp-aes";
167      };
168
169      versal_clk: clock-controller {
170        #clock-cells = <1>;
171        compatible = "xlnx,versal-clk";
172        clocks = <&ref>, <&pl_alt_ref>;
173        clock-names = "ref", "pl_alt_ref";
174      };
175    };
176
177...
178