1*0e79cb70STimo AlhoNVIDIA Tegra210 Boot and Power Management Processor (BPMP) 2*0e79cb70STimo Alho 3*0e79cb70STimo AlhoThe Boot and Power Management Processor (BPMP) is a co-processor found 4*0e79cb70STimo Alhoin Tegra210 SoC. It is designed to handle the early stages of the boot 5*0e79cb70STimo Alhoprocess as well as to assisting in entering deep low power state 6*0e79cb70STimo Alho(suspend to ram), and also offloading DRAM memory clock scaling on 7*0e79cb70STimo Alhosome platforms. The binding document defines the resources that would 8*0e79cb70STimo Alhobe used by the BPMP T210 firmware driver, which can create the 9*0e79cb70STimo Alhointerprocessor communication (IPC) between the CPU and BPMP. 10*0e79cb70STimo Alho 11*0e79cb70STimo AlhoRequired properties: 12*0e79cb70STimo Alho- compatible 13*0e79cb70STimo Alho Array of strings 14*0e79cb70STimo Alho One of: 15*0e79cb70STimo Alho - "nvidia,tegra210-bpmp" 16*0e79cb70STimo Alho- reg: physical base address and length for HW synchornization primitives 17*0e79cb70STimo Alho 1) base address and length to Tegra 'atomics' hardware 18*0e79cb70STimo Alho 2) base address and length to Tegra 'semaphore' hardware 19*0e79cb70STimo Alho- interrupts: specifies the interrupt number for receiving messages ("rx") 20*0e79cb70STimo Alho and for triggering messages ("tx") 21*0e79cb70STimo Alho 22*0e79cb70STimo AlhoOptional properties: 23*0e79cb70STimo Alho- #clock-cells : Should be 1 for platforms where DRAM clock control is 24*0e79cb70STimo Alho offloaded to bpmp. 25*0e79cb70STimo Alho 26*0e79cb70STimo AlhoExample: 27*0e79cb70STimo Alho 28*0e79cb70STimo Alhobpmp@70016000 { 29*0e79cb70STimo Alho compatible = "nvidia,tegra210-bpmp"; 30*0e79cb70STimo Alho reg = <0x0 0x70016000 0x0 0x2000 31*0e79cb70STimo Alho 0x0 0x60001000 0x0 0x1000>; 32*0e79cb70STimo Alho interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>, 33*0e79cb70STimo Alho <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 34*0e79cb70STimo Alho interrupt-names = "tx", "rx"; 35*0e79cb70STimo Alho}; 36