1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP i.MX System Controller Firmware (SCFW) 8 9maintainers: 10 - Dong Aisheng <aisheng.dong@nxp.com> 11 12description: 13 The System Controller Firmware (SCFW) is a low-level system function 14 which runs on a dedicated Cortex-M core to provide power, clock, and 15 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM 16 (QM, QP), and i.MX8QX (QXP, DX). 17 The AP communicates with the SC using a multi-ported MU module found 18 in the LSIO subsystem. The current definition of this MU module provides 19 5 remote AP connections to the SC to support up to 5 execution environments 20 (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces 21 with the LSIO DSC IP bus. The SC firmware will communicate with this MU 22 using the MSI bus. 23 24properties: 25 compatible: 26 const: fsl,imx-scu 27 28 clock-controller: 29 description: 30 Clock controller node that provides the clocks controlled by the SCU 31 $ref: /schemas/clock/fsl,scu-clk.yaml 32 33 gpio: 34 description: 35 Control the GPIO PINs on SCU domain over the firmware APIs 36 $ref: /schemas/gpio/fsl,imx8qxp-sc-gpio.yaml 37 38 ocotp: 39 description: 40 OCOTP controller node provided by the SCU 41 $ref: /schemas/nvmem/fsl,scu-ocotp.yaml 42 43 keys: 44 description: 45 Keys provided by the SCU 46 $ref: /schemas/input/fsl,scu-key.yaml 47 48 reset-controller: 49 type: object 50 properties: 51 compatible: 52 const: fsl,imx-scu-reset 53 '#reset-cells': 54 const: 1 55 required: 56 - compatible 57 - '#reset-cells' 58 additionalProperties: false 59 60 mboxes: 61 description: 62 A list of phandles of TX MU channels followed by a list of phandles of 63 RX MU channels. The list may include at the end one more optional MU 64 channel for general interrupt. The number of expected tx and rx 65 channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu" 66 compatible, 4 TX and 4 RX channels otherwise. All MU channels must be 67 within the same MU instance. Cross instances are not allowed. The MU 68 instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users 69 need to ensure that one is used that does not conflict with other 70 execution environments such as ATF. 71 oneOf: 72 - items: 73 - description: TX0 MU channel 74 - description: RX0 MU channel 75 - items: 76 - description: TX0 MU channel 77 - description: RX0 MU channel 78 - description: optional MU channel for general interrupt 79 - deprecated: true 80 items: 81 - description: TX0 MU channel 82 - description: TX1 MU channel 83 - description: TX2 MU channel 84 - description: TX3 MU channel 85 - description: RX0 MU channel 86 - description: RX1 MU channel 87 - description: RX2 MU channel 88 - description: RX3 MU channel 89 - deprecated: true 90 items: 91 - description: TX0 MU channel 92 - description: TX1 MU channel 93 - description: TX2 MU channel 94 - description: TX3 MU channel 95 - description: RX0 MU channel 96 - description: RX1 MU channel 97 - description: RX2 MU channel 98 - description: RX3 MU channel 99 - description: optional MU channel for general interrupt 100 101 mbox-names: 102 oneOf: 103 - items: 104 - const: tx0 105 - const: rx0 106 - items: 107 - const: tx0 108 - const: rx0 109 - const: gip3 110 - deprecated: true 111 items: 112 - const: tx0 113 - const: tx1 114 - const: tx2 115 - const: tx3 116 - const: rx0 117 - const: rx1 118 - const: rx2 119 - const: rx3 120 - deprecated: true 121 items: 122 - const: tx0 123 - const: tx1 124 - const: tx2 125 - const: tx3 126 - const: rx0 127 - const: rx1 128 - const: rx2 129 - const: rx3 130 - const: gip3 131 132 pinctrl: 133 description: 134 Pin controller provided by the SCU 135 $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml 136 137 power-controller: 138 description: 139 Power domains controller node that provides the power domains 140 controlled by the SCU 141 $ref: /schemas/power/fsl,scu-pd.yaml 142 143 rtc: 144 description: 145 RTC controller provided by the SCU 146 $ref: /schemas/rtc/fsl,scu-rtc.yaml 147 148 thermal-sensor: 149 description: 150 Thermal sensor provided by the SCU 151 $ref: /schemas/thermal/fsl,scu-thermal.yaml 152 153 watchdog: 154 description: 155 Watchdog controller provided by the SCU 156 $ref: /schemas/watchdog/fsl,scu-wdt.yaml 157 158required: 159 - compatible 160 - mbox-names 161 - mboxes 162 163additionalProperties: false 164 165examples: 166 - | 167 #include <dt-bindings/firmware/imx/rsrc.h> 168 #include <dt-bindings/input/input.h> 169 #include <dt-bindings/pinctrl/pads-imx8qxp.h> 170 171 firmware { 172 system-controller { 173 compatible = "fsl,imx-scu"; 174 mbox-names = "tx0", "rx0", "gip3"; 175 mboxes = <&lsio_mu1 0 0 176 &lsio_mu1 1 0 177 &lsio_mu1 3 3>; 178 179 clock-controller { 180 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 181 #clock-cells = <2>; 182 }; 183 184 pinctrl { 185 compatible = "fsl,imx8qxp-iomuxc"; 186 187 pinctrl_lpuart0: lpuart0grp { 188 fsl,pins = < 189 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 190 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 191 >; 192 }; 193 }; 194 195 ocotp { 196 compatible = "fsl,imx8qxp-scu-ocotp"; 197 #address-cells = <1>; 198 #size-cells = <1>; 199 200 fec_mac0: mac@2c4 { 201 reg = <0x2c4 6>; 202 }; 203 }; 204 205 power-controller { 206 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 207 #power-domain-cells = <1>; 208 }; 209 210 rtc { 211 compatible = "fsl,imx8qxp-sc-rtc"; 212 }; 213 214 keys { 215 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 216 linux,keycodes = <KEY_POWER>; 217 }; 218 219 watchdog { 220 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 221 timeout-sec = <60>; 222 }; 223 224 thermal-sensor { 225 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 226 #thermal-sensor-cells = <1>; 227 }; 228 }; 229 }; 230