1Aspeed BMC SoC EDAC node 2 3The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error 4correction check). 5 6The memory controller supports SECDED (single bit error correction, double bit 7error detection) and single bit error auto scrubbing by reserving 8 bits for 8every 64 bit word (effectively reducing available memory to 8/9). 9 10Note, the bootloader must configure ECC mode in the memory controller. 11 12 13Required properties: 14- compatible: should be one of 15 - "aspeed,ast2400-sdram-edac" 16 - "aspeed,ast2500-sdram-edac" 17 - "aspeed,ast2600-sdram-edac" 18- reg: sdram controller register set should be <0x1e6e0000 0x174> 19- interrupts: should be AVIC interrupt #0 20 21 22Example: 23 24 edac: sdram@1e6e0000 { 25 compatible = "aspeed,ast2500-sdram-edac"; 26 reg = <0x1e6e0000 0x174>; 27 interrupts = <0>; 28 }; 29