xref: /linux/Documentation/devicetree/bindings/dvfs/performance-domain.yaml (revision fd7d598270724cc787982ea48bbe17ad383a8b7f) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic performance domains
8
9maintainers:
10  - Sudeep Holla <sudeep.holla@arm.com>
11
12description: |+
13  This binding is intended for performance management of groups of devices or
14  CPUs that run in the same performance domain. Performance domains must not
15  be confused with power domains. A performance domain is defined by a set
16  of devices that always have to run at the same performance level. For a given
17  performance domain, there is a single point of control that affects all the
18  devices in the domain, making it impossible to set the performance level of
19  an individual device in the domain independently from other devices in
20  that domain. For example, a set of CPUs that share a voltage domain, and
21  have a common frequency control, is said to be in the same performance
22  domain.
23
24  This device tree binding can be used to bind performance domain consumer
25  devices with their performance domains provided by performance domain
26  providers. A performance domain provider can be represented by any node in
27  the device tree and can provide one or more performance domains. A consumer
28  node can refer to the provider by a phandle and a set of phandle arguments
29  (so called performance domain specifiers) of length specified by the
30  \#performance-domain-cells property in the performance domain provider node.
31
32select: true
33
34properties:
35  "#performance-domain-cells":
36    description:
37      Number of cells in a performance domain specifier. Typically 0 for nodes
38      representing a single performance domain and 1 for nodes providing
39      multiple performance domains (e.g. performance controllers), but can be
40      any value as specified by device tree binding documentation of particular
41      provider.
42    enum: [ 0, 1 ]
43
44  performance-domains:
45    $ref: /schemas/types.yaml#/definitions/phandle-array
46    description:
47      A phandle and performance domain specifier as defined by bindings of the
48      performance controller/provider specified by phandle.
49
50additionalProperties: true
51
52examples:
53  - |
54    soc {
55        #address-cells = <2>;
56        #size-cells = <2>;
57
58        performance: performance-controller@11bc00 {
59            compatible = "mediatek,cpufreq-hw";
60            reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
61
62            #performance-domain-cells = <1>;
63        };
64    };
65
66    // The node above defines a performance controller that is a performance
67    // domain provider and expects one cell as its phandle argument.
68
69    cpus {
70        #address-cells = <2>;
71        #size-cells = <0>;
72
73        cpu@0 {
74            device_type = "cpu";
75            compatible = "arm,cortex-a57";
76            reg = <0x0 0x0>;
77            performance-domains = <&performance 1>;
78        };
79    };
80