xref: /linux/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml (revision fc2d791a43d3880496d1c729b8bd74d2c19cb4e7) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip Azurite DPLL device
8
9maintainers:
10  - Ivan Vecera <ivecera@redhat.com>
11
12description:
13  Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
14  provides up to 5 independent DPLL channels, up to 10 differential or
15  single-ended inputs and 10 differential or 20 single-ended outputs.
16  These devices support both I2C and SPI interfaces.
17
18properties:
19  compatible:
20    enum:
21      - microchip,zl30731
22      - microchip,zl30732
23      - microchip,zl30733
24      - microchip,zl30734
25      - microchip,zl30735
26
27  reg:
28    maxItems: 1
29
30required:
31  - compatible
32  - reg
33
34allOf:
35  - $ref: /schemas/dpll/dpll-device.yaml#
36  - $ref: /schemas/spi/spi-peripheral-props.yaml#
37
38unevaluatedProperties: false
39
40examples:
41  - |
42    i2c {
43      #address-cells = <1>;
44      #size-cells = <0>;
45
46      dpll@70 {
47        compatible = "microchip,zl30732";
48        reg = <0x70>;
49        dpll-types = "pps", "eec";
50
51        input-pins {
52          #address-cells = <1>;
53          #size-cells = <0>;
54
55          sync0: pin@0 { /* REF0P - 1 PPS sync source */
56            reg = <0>;
57            connection-type = "ext";
58            label = "SMA1";
59            supported-frequencies-hz = /bits/ 64 <1>;
60          };
61
62          pin@1 { /* REF0N - clock source, can pair with sync0 */
63            reg = <1>;
64            connection-type = "ext";
65            label = "SMA2";
66            supported-frequencies-hz = /bits/ 64 <10000 10000000>;
67            ref-sync-sources = <&sync0>;
68          };
69        };
70
71        output-pins {
72          #address-cells = <1>;
73          #size-cells = <0>;
74
75          pin@3 { /* OUT1N */
76            reg = <3>;
77            connection-type = "gnss";
78            esync-control;
79            label = "Output 1";
80            supported-frequencies-hz = /bits/ 64 <1 10000>;
81          };
82        };
83      };
84    };
85  - |
86    spi {
87      #address-cells = <1>;
88      #size-cells = <0>;
89
90      dpll@70 {
91        compatible = "microchip,zl30731";
92        reg = <0x70>;
93        spi-max-frequency = <12500000>;
94
95        dpll-types = "pps";
96
97        input-pins {
98          #address-cells = <1>;
99          #size-cells = <0>;
100
101          sync1: pin@0 { /* REF0P - 1 PPS sync source */
102            reg = <0>;
103            connection-type = "gnss";
104            label = "GNSS_1PPS_IN";
105            supported-frequencies-hz = /bits/ 64 <1>;
106          };
107
108          pin@1 { /* REF0N - clock source */
109            reg = <1>;
110            connection-type = "gnss";
111            label = "GNSS_10M_IN";
112            supported-frequencies-hz = /bits/ 64 <10000000>;
113            ref-sync-sources = <&sync1>;
114          };
115        };
116
117        output-pins {
118          #address-cells = <1>;
119          #size-cells = <0>;
120
121          pin@3 { /* OUT1N */
122            reg = <3>;
123            connection-type = "gnss";
124            esync-control;
125            label = "Output 1";
126            supported-frequencies-hz = /bits/ 64 <1 10000>;
127          };
128        };
129      };
130    };
131...
132