1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/dpll/dpll-pin.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: DPLL Pin 8 9maintainers: 10 - Ivan Vecera <ivecera@redhat.com> 11 12description: | 13 The DPLL pin is either a physical input or output pin that is provided 14 by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by 15 its physical order number that is stored in reg property and can have 16 an additional set of properties like supported (allowed) frequencies, 17 label, type and may support embedded sync. 18 19 Note that the pin in this context has nothing to do with pinctrl. 20 21properties: 22 reg: 23 description: Hardware index of the DPLL pin. 24 maxItems: 1 25 26 connection-type: 27 description: Connection type of the pin 28 $ref: /schemas/types.yaml#/definitions/string 29 enum: [ext, gnss, int, mux, synce] 30 31 esync-control: 32 description: Indicates whether the pin supports embedded sync functionality. 33 type: boolean 34 35 label: 36 description: String exposed as the pin board label 37 $ref: /schemas/types.yaml#/definitions/string 38 39 ref-sync-sources: 40 description: | 41 List of phandles to input pins that can serve as the sync source 42 in a Reference-Sync pair with this pin acting as the clock source. 43 A Ref-Sync pair consists of a clock reference and a low-frequency 44 sync signal. The DPLL locks to the clock reference but 45 phase-aligns to the sync reference. 46 Only valid for input pins. Each referenced pin must be a 47 different input pin on the same device. 48 $ref: /schemas/types.yaml#/definitions/phandle-array 49 items: 50 maxItems: 1 51 52 supported-frequencies-hz: 53 description: List of supported frequencies for this pin, expressed in Hz. 54 55required: 56 - reg 57 58additionalProperties: false 59