xref: /linux/Documentation/devicetree/bindings/dpll/dpll-device.yaml (revision 4a774b39e68fac7d6c7c9cffeb6a4ea4b6dc8b41) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Digital Phase-Locked Loop (DPLL) Device
8
9maintainers:
10  - Ivan Vecera <ivecera@redhat.com>
11
12description:
13  Digital Phase-Locked Loop (DPLL) device is used for precise clock
14  synchronization in networking and telecom hardware. The device can
15  have one or more channels (DPLLs) and one or more physical input and
16  output pins. Each DPLL channel can either produce pulse-per-clock signal
17  or drive ethernet equipment clock. The type of each channel can be
18  indicated by dpll-types property.
19
20properties:
21  $nodename:
22    pattern: "^dpll(@.*)?$"
23
24  "#address-cells":
25    const: 0
26
27  "#size-cells":
28    const: 0
29
30  dpll-types:
31    description: List of DPLL channel types, one per DPLL instance.
32    $ref: /schemas/types.yaml#/definitions/non-unique-string-array
33    items:
34      enum: [pps, eec]
35
36  input-pins:
37    type: object
38    description: DPLL input pins
39    unevaluatedProperties: false
40
41    properties:
42      "#address-cells":
43        const: 1
44      "#size-cells":
45        const: 0
46
47    patternProperties:
48      "^pin@[0-9a-f]+$":
49        $ref: /schemas/dpll/dpll-pin.yaml
50        unevaluatedProperties: false
51
52    required:
53      - "#address-cells"
54      - "#size-cells"
55
56  output-pins:
57    type: object
58    description: DPLL output pins
59    unevaluatedProperties: false
60
61    properties:
62      "#address-cells":
63        const: 1
64      "#size-cells":
65        const: 0
66
67    patternProperties:
68      "^pin@[0-9]+$":
69        $ref: /schemas/dpll/dpll-pin.yaml
70        unevaluatedProperties: false
71
72    required:
73      - "#address-cells"
74      - "#size-cells"
75
76additionalProperties: true
77