1Xilinx AXI VDMA engine, it does transfers between memory and video devices. 2It can be configured to have one channel or two channels. If configured 3as two channels, one is to transmit to the video device and another is 4to receive from the video device. 5 6Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream 7target devices. It can be configured to have one channel or two channels. 8If configured as two channels, one is to transmit to the device and another 9is to receive from the device. 10 11Xilinx AXI CDMA engine, it does transfers between memory-mapped source 12address and a memory-mapped destination address. 13 14Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream 15target devices. It can be configured to have up to 16 independent transmit 16and receive channels. 17 18Required properties: 19- compatible: Should be one of- 20 "xlnx,axi-vdma-1.00.a" 21 "xlnx,axi-dma-1.00.a" 22 "xlnx,axi-cdma-1.00.a" 23 "xlnx,axi-mcdma-1.00.a" 24- #dma-cells: Should be <1>, see "dmas" property below 25- reg: Should contain VDMA registers location and length. 26- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). 27- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>. 28- dma-channel child node: Should have at least one channel and can have up to 29 two channels per device. This node specifies the properties of each 30 DMA channel (see child node properties below). 31- clocks: Input clock specifier. Refer to common clock bindings. 32- clock-names: List of input clocks 33 For VDMA: 34 Required elements: "s_axi_lite_aclk" 35 Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk", 36 "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" 37 For CDMA: 38 Required elements: "s_axi_lite_aclk", "m_axi_aclk" 39 For AXIDMA and MCDMA: 40 Required elements: "s_axi_lite_aclk" 41 Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", 42 "m_axi_sg_aclk" 43 44Required properties for VDMA: 45- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. 46 47Optional properties for AXI DMA and MCDMA: 48- xlnx,sg-length-width: Should be set to the width in bits of the length 49 register as configured in h/w. Takes values {8...26}. If the property 50 is missing or invalid then the default value 23 is used. This is the 51 maximum value that is supported by all IP versions. 52 53Optional properties for AXI DMA: 54- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP. 55- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from 56 0-255. Setting this value to zero disables the delay timer interrupt. 57 1 timeout interval = 125 * clock period of SG clock. 58Optional properties for VDMA: 59- xlnx,flush-fsync: Tells which channel to Flush on Frame sync. 60 It takes following values: 61 {1}, flush both channels 62 {2}, flush mm2s channel 63 {3}, flush s2mm channel 64 65Required child node properties: 66- compatible: 67 For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or 68 "xlnx,axi-vdma-s2mm-channel". 69 For CDMA: It should be "xlnx,axi-cdma-channel". 70 For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel" 71 or "xlnx,axi-dma-s2mm-channel". 72- interrupts: Should contain per channel VDMA interrupts. 73- xlnx,datawidth: Should contain the stream data width, take values 74 {32,64...1024}. 75 76Optional child node properties: 77- xlnx,include-dre: Tells hardware is configured for Data 78 Realignment Engine. 79Optional child node properties for VDMA: 80- xlnx,genlock-mode: Tells Genlock synchronization is 81 enabled/disabled in hardware. 82- xlnx,enable-vert-flip: Tells vertical flip is 83 enabled/disabled in hardware(S2MM path). 84Optional child node properties for MCDMA: 85- dma-channels: Number of dma channels in child node. 86 87Example: 88++++++++ 89 90axi_vdma_0: axivdma@40030000 { 91 compatible = "xlnx,axi-vdma-1.00.a"; 92 #dma_cells = <1>; 93 reg = < 0x40030000 0x10000 >; 94 dma-ranges = <0x00000000 0x00000000 0x40000000>; 95 xlnx,num-fstores = <0x8>; 96 xlnx,flush-fsync = <0x1>; 97 xlnx,addrwidth = <0x20>; 98 clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; 99 clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", 100 "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; 101 dma-channel@40030000 { 102 compatible = "xlnx,axi-vdma-mm2s-channel"; 103 interrupts = < 0 54 4 >; 104 xlnx,datawidth = <0x40>; 105 } ; 106 dma-channel@40030030 { 107 compatible = "xlnx,axi-vdma-s2mm-channel"; 108 interrupts = < 0 53 4 >; 109 xlnx,datawidth = <0x40>; 110 } ; 111} ; 112 113 114* DMA client 115 116Required properties: 117- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, 118 where Channel ID is '0' for write/tx and '1' for read/rx 119 channel. For MCMDA, MM2S channel(write/tx) ID start from 120 '0' and is in [0-15] range. S2MM channel(read/rx) ID start 121 from '16' and is in [16-31] range. These channels ID are 122 fixed irrespective of IP configuration. 123 124- dma-names: a list of DMA channel names, one per "dmas" entry 125 126Example: 127++++++++ 128 129vdmatest_0: vdmatest@0 { 130 compatible ="xlnx,axi-vdma-test-1.00.a"; 131 dmas = <&axi_vdma_0 0 132 &axi_vdma_0 1>; 133 dma-names = "vdma0", "vdma1"; 134} ; 135