1*897f419aSPeter Griffin* STMicroelectronics Flexible Direct Memory Access Device Tree bindings 2*897f419aSPeter Griffin 3*897f419aSPeter GriffinThe FDMA is a general-purpose direct memory access controller capable of 4*897f419aSPeter Griffinsupporting 16 independent DMA channels. It accepts up to 32 DMA requests. 5*897f419aSPeter GriffinThe FDMA is based on a Slim processor which requires a firmware. 6*897f419aSPeter Griffin 7*897f419aSPeter Griffin* FDMA Controller 8*897f419aSPeter Griffin 9*897f419aSPeter GriffinRequired properties: 10*897f419aSPeter Griffin- compatible : Should be one of 11*897f419aSPeter Griffin - st,stih407-fdma-mpe31-11, "st,slim-rproc"; 12*897f419aSPeter Griffin - st,stih407-fdma-mpe31-12, "st,slim-rproc"; 13*897f419aSPeter Griffin - st,stih407-fdma-mpe31-13, "st,slim-rproc"; 14*897f419aSPeter Griffin- reg : Should contain an entry for each name in reg-names 15*897f419aSPeter Griffin- reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries 16*897f419aSPeter Griffin- interrupts : Should contain one interrupt shared by all channels 17*897f419aSPeter Griffin- dma-channels : Number of channels supported by the controller 18*897f419aSPeter Griffin- #dma-cells : Must be <3>. See DMA client section below 19*897f419aSPeter Griffin- clocks : Must contain an entry for each clock 20*897f419aSPeter GriffinSee: Documentation/devicetree/bindings/clock/clock-bindings.txt 21*897f419aSPeter Griffin 22*897f419aSPeter Griffin 23*897f419aSPeter GriffinExample: 24*897f419aSPeter Griffin 25*897f419aSPeter Griffin fdma0: dma-controller@8e20000 { 26*897f419aSPeter Griffin compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; 27*897f419aSPeter Griffin reg = <0x8e20000 0x8000>, 28*897f419aSPeter Griffin <0x8e30000 0x3000>, 29*897f419aSPeter Griffin <0x8e37000 0x1000>, 30*897f419aSPeter Griffin <0x8e38000 0x8000>; 31*897f419aSPeter Griffin reg-names = "slimcore", "dmem", "peripherals", "imem"; 32*897f419aSPeter Griffin clocks = <&clk_s_c0_flexgen CLK_FDMA>, 33*897f419aSPeter Griffin <&clk_s_c0_flexgen CLK_EXT2F_A9>, 34*897f419aSPeter Griffin <&clk_s_c0_flexgen CLK_EXT2F_A9>, 35*897f419aSPeter Griffin <&clk_s_c0_flexgen CLK_EXT2F_A9>; 36*897f419aSPeter Griffin interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>; 37*897f419aSPeter Griffin dma-channels = <16>; 38*897f419aSPeter Griffin #dma-cells = <3>; 39*897f419aSPeter Griffin }; 40*897f419aSPeter Griffin 41*897f419aSPeter Griffin* DMA client 42*897f419aSPeter Griffin 43*897f419aSPeter GriffinRequired properties: 44*897f419aSPeter Griffin- dmas: Comma separated list of dma channel requests 45*897f419aSPeter Griffin- dma-names: Names of the aforementioned requested channels 46*897f419aSPeter Griffin 47*897f419aSPeter GriffinEach dmas request consists of 4 cells: 48*897f419aSPeter Griffin1. A phandle pointing to the FDMA controller 49*897f419aSPeter Griffin2. The request line number 50*897f419aSPeter Griffin3. A 32bit mask specifying (see include/linux/platform_data/dma-st-fdma.h) 51*897f419aSPeter Griffin -bit 2-0: Holdoff value, dreq will be masked for 52*897f419aSPeter Griffin 0x0: 0-0.5us 53*897f419aSPeter Griffin 0x1: 0.5-1us 54*897f419aSPeter Griffin 0x2: 1-1.5us 55*897f419aSPeter Griffin -bit 17: data swap 56*897f419aSPeter Griffin 0x0: disabled 57*897f419aSPeter Griffin 0x1: enabled 58*897f419aSPeter Griffin -bit 21: Increment Address 59*897f419aSPeter Griffin 0x0: no address increment between transfers 60*897f419aSPeter Griffin 0x1: increment address between transfers 61*897f419aSPeter Griffin -bit 22: 2 STBus Initiator Coprocessor interface 62*897f419aSPeter Griffin 0x0: high priority port 63*897f419aSPeter Griffin 0x1: low priority port 64*897f419aSPeter Griffin4. transfers type 65*897f419aSPeter Griffin 0 free running 66*897f419aSPeter Griffin 1 paced 67*897f419aSPeter Griffin 68*897f419aSPeter GriffinExample: 69*897f419aSPeter Griffin 70*897f419aSPeter Griffin sti_uni_player2: sti-uni-player@2 { 71*897f419aSPeter Griffin compatible = "st,sti-uni-player"; 72*897f419aSPeter Griffin status = "disabled"; 73*897f419aSPeter Griffin #sound-dai-cells = <0>; 74*897f419aSPeter Griffin st,syscfg = <&syscfg_core>; 75*897f419aSPeter Griffin clocks = <&clk_s_d0_flexgen CLK_PCM_2>; 76*897f419aSPeter Griffin assigned-clocks = <&clk_s_d0_flexgen CLK_PCM_2>; 77*897f419aSPeter Griffin assigned-clock-parents = <&clk_s_d0_quadfs 2>; 78*897f419aSPeter Griffin assigned-clock-rates = <50000000>; 79*897f419aSPeter Griffin reg = <0x8D82000 0x158>; 80*897f419aSPeter Griffin interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; 81*897f419aSPeter Griffin dmas = <&fdma0 4 0 1>; 82*897f419aSPeter Griffin dai-name = "Uni Player #1 (DAC)"; 83*897f419aSPeter Griffin dma-names = "tx"; 84*897f419aSPeter Griffin st,uniperiph-id = <2>; 85*897f419aSPeter Griffin st,version = <5>; 86*897f419aSPeter Griffin st,mode = "PCM"; 87*897f419aSPeter Griffin }; 88