xref: /linux/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml (revision 64b14a184e83eb62ea0615e31a409956049d40e7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare AXI DMA Controller
8
9maintainers:
10  - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
11  - Jee Heng Sia <jee.heng.sia@intel.com>
12
13description:
14  Synopsys DesignWare AXI DMA Controller DT Binding
15
16allOf:
17  - $ref: "dma-controller.yaml#"
18
19properties:
20  compatible:
21    enum:
22      - snps,axi-dma-1.01a
23      - intel,kmb-axi-dma
24
25  reg:
26    minItems: 1
27    items:
28      - description: Address range of the DMAC registers
29      - description: Address range of the DMAC APB registers
30
31  reg-names:
32    items:
33      - const: axidma_ctrl_regs
34      - const: axidma_apb_regs
35
36  interrupts:
37    maxItems: 1
38
39  clocks:
40    items:
41      - description: Bus Clock
42      - description: Module Clock
43
44  clock-names:
45    items:
46      - const: core-clk
47      - const: cfgr-clk
48
49  '#dma-cells':
50    const: 1
51
52  dma-channels:
53    minimum: 1
54    maximum: 8
55
56  resets:
57    maxItems: 1
58
59  snps,dma-masters:
60    description: |
61      Number of AXI masters supported by the hardware.
62    $ref: /schemas/types.yaml#/definitions/uint32
63    enum: [1, 2]
64
65  snps,data-width:
66    description: |
67      AXI data width supported by hardware.
68      (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
69    $ref: /schemas/types.yaml#/definitions/uint32
70    enum: [0, 1, 2, 3, 4, 5, 6]
71
72  snps,priority:
73    description: |
74      Channel priority specifier associated with the DMA channels.
75    $ref: /schemas/types.yaml#/definitions/uint32-array
76    minItems: 1
77    maxItems: 8
78
79  snps,block-size:
80    description: |
81      Channel block size specifier associated with the DMA channels.
82    $ref: /schemas/types.yaml#/definitions/uint32-array
83    minItems: 1
84    maxItems: 8
85
86  snps,axi-max-burst-len:
87    description: |
88      Restrict master AXI burst length by value specified in this property.
89      If this property is missing the maximum AXI burst length supported by
90      DMAC is used.
91    $ref: /schemas/types.yaml#/definitions/uint32
92    minimum: 1
93    maximum: 256
94
95required:
96  - compatible
97  - reg
98  - clocks
99  - clock-names
100  - interrupts
101  - '#dma-cells'
102  - dma-channels
103  - snps,dma-masters
104  - snps,data-width
105  - snps,priority
106  - snps,block-size
107
108additionalProperties: false
109
110examples:
111  - |
112     #include <dt-bindings/interrupt-controller/arm-gic.h>
113     #include <dt-bindings/interrupt-controller/irq.h>
114     /* example with snps,dw-axi-dmac */
115     dmac: dma-controller@80000 {
116         compatible = "snps,axi-dma-1.01a";
117         reg = <0x80000 0x400>;
118         clocks = <&core_clk>, <&cfgr_clk>;
119         clock-names = "core-clk", "cfgr-clk";
120         interrupt-parent = <&intc>;
121         interrupts = <27>;
122         #dma-cells = <1>;
123         dma-channels = <4>;
124         snps,dma-masters = <2>;
125         snps,data-width = <3>;
126         snps,block-size = <4096 4096 4096 4096>;
127         snps,priority = <0 1 2 3>;
128         snps,axi-max-burst-len = <16>;
129     };
130