xref: /linux/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml (revision 58d416351e6df1a41d415958ccdd8eb9c2173fed) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys Designware DMA Controller
8
9maintainers:
10  - Viresh Kumar <vireshk@kernel.org>
11  - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
12
13allOf:
14  - $ref: "dma-controller.yaml#"
15
16properties:
17  compatible:
18    const: snps,dma-spear1340
19
20  "#dma-cells":
21    minimum: 3
22    maximum: 4
23    description: |
24      First cell is a phandle pointing to the DMA controller. Second one is
25      the DMA request line number. Third cell is the memory master identifier
26      for transfers on dynamically allocated channel. Fourth cell is the
27      peripheral master identifier for transfers on an allocated channel. Fifth
28      cell is an optional mask of the DMA channels permitted to be allocated
29      for the corresponding client device.
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    maxItems: 1
36
37  clocks:
38    maxItems: 1
39
40  clock-names:
41    description: AHB interface reference clock.
42    const: hclk
43
44  dma-channels:
45    description: |
46      Number of DMA channels supported by the controller. In case if
47      not specified the driver will try to auto-detect this and
48      the rest of the optional parameters.
49    minimum: 1
50    maximum: 8
51
52  dma-requests:
53    minimum: 1
54    maximum: 16
55
56  dma-masters:
57    $ref: /schemas/types.yaml#/definitions/uint32
58    description: |
59      Number of DMA masters supported by the controller. In case if
60      not specified the driver will try to auto-detect this and
61      the rest of the optional parameters.
62    minimum: 1
63    maximum: 4
64
65  chan_allocation_order:
66    $ref: /schemas/types.yaml#/definitions/uint32
67    description: |
68      DMA channels allocation order specifier. Zero means ascending order
69      (first free allocated), while one - descending (last free allocated).
70    default: 0
71    enum: [0, 1]
72
73  chan_priority:
74    $ref: /schemas/types.yaml#/definitions/uint32
75    description: |
76      DMA channels priority order. Zero means ascending channels priority
77      so the very first channel has the highest priority. While 1 means
78      descending priority (the last channel has the highest priority).
79    default: 0
80    enum: [0, 1]
81
82  block_size:
83    $ref: /schemas/types.yaml#/definitions/uint32
84    description: Maximum block size supported by the DMA controller.
85    enum: [3, 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095]
86
87  data-width:
88    $ref: /schemas/types.yaml#/definitions/uint32-array
89    description: Data bus width per each DMA master in bytes.
90    items:
91      maxItems: 4
92      items:
93        enum: [4, 8, 16, 32]
94
95  data_width:
96    $ref: /schemas/types.yaml#/definitions/uint32-array
97    deprecated: true
98    description: |
99      Data bus width per each DMA master in (2^n * 8) bits. This property is
100      deprecated. It' usage is discouraged in favor of data-width one. Moreover
101      the property incorrectly permits to define data-bus width of 8 and 16
102      bits, which is impossible in accordance with DW DMAC IP-core data book.
103    items:
104      maxItems: 4
105      items:
106        enum:
107          - 0 # 8 bits
108          - 1 # 16 bits
109          - 2 # 32 bits
110          - 3 # 64 bits
111          - 4 # 128 bits
112          - 5 # 256 bits
113        default: 0
114
115  multi-block:
116    $ref: /schemas/types.yaml#/definitions/uint32-array
117    description: |
118      LLP-based multi-block transfer supported by hardware per
119      each DMA channel.
120    items:
121      maxItems: 8
122      items:
123        enum: [0, 1]
124        default: 1
125
126  snps,max-burst-len:
127    $ref: /schemas/types.yaml#/definitions/uint32-array
128    description: |
129      Maximum length of the burst transactions supported by the controller.
130      This property defines the upper limit of the run-time burst setting
131      (CTLx.SRC_MSIZE/CTLx.DST_MSIZE fields) so the allowed burst length
132      will be from 1 to max-burst-len words. It's an array property with one
133      cell per channel in the units determined by the value set in the
134      CTLx.SRC_TR_WIDTH/CTLx.DST_TR_WIDTH fields (data width).
135    items:
136      maxItems: 8
137      items:
138        enum: [4, 8, 16, 32, 64, 128, 256]
139        default: 256
140
141  snps,dma-protection-control:
142    $ref: /schemas/types.yaml#/definitions/uint32
143    description: |
144      Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting
145      indicates the following features: bit 0 - privileged mode,
146      bit 1 - DMA is bufferable, bit 2 - DMA is cacheable.
147    default: 0
148    minimum: 0
149    maximum: 7
150
151unevaluatedProperties: false
152
153required:
154  - compatible
155  - "#dma-cells"
156  - reg
157  - interrupts
158
159examples:
160  - |
161    dma-controller@fc000000 {
162      compatible = "snps,dma-spear1340";
163      reg = <0xfc000000 0x1000>;
164      interrupt-parent = <&vic1>;
165      interrupts = <12>;
166
167      dma-channels = <8>;
168      dma-requests = <16>;
169      dma-masters = <4>;
170      #dma-cells = <3>;
171
172      chan_allocation_order = <1>;
173      chan_priority = <1>;
174      block_size = <0xfff>;
175      data-width = <8 8>;
176      multi-block = <0 0 0 0 0 0 0 0>;
177      snps,max-burst-len = <16 16 4 4 4 4 4 4>;
178    };
179...
180