1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ DMA Controller 8 9maintainers: 10 - Biju Das <biju.das.jz@bp.renesas.com> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - renesas,r7s72100-dmac # RZ/A1H 17 - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five 18 - renesas,r9a07g044-dmac # RZ/G2{L,LC} 19 - renesas,r9a07g054-dmac # RZ/V2L 20 - renesas,r9a08g045-dmac # RZ/G3S 21 - const: renesas,rz-dmac 22 23 reg: 24 items: 25 - description: Control and channel register block 26 - description: DMA extended resource selector block 27 28 interrupts: 29 maxItems: 17 30 31 interrupt-names: 32 items: 33 - const: error 34 - const: ch0 35 - const: ch1 36 - const: ch2 37 - const: ch3 38 - const: ch4 39 - const: ch5 40 - const: ch6 41 - const: ch7 42 - const: ch8 43 - const: ch9 44 - const: ch10 45 - const: ch11 46 - const: ch12 47 - const: ch13 48 - const: ch14 49 - const: ch15 50 51 clocks: 52 items: 53 - description: DMA main clock 54 - description: DMA register access clock 55 56 clock-names: 57 items: 58 - const: main 59 - const: register 60 61 '#dma-cells': 62 const: 1 63 description: 64 The cell specifies the encoded MID/RID values of the DMAC port 65 connected to the DMA client and the slave channel configuration 66 parameters. 67 bits[0:9] - Specifies MID/RID value 68 bit[10] - Specifies DMA request high enable (HIEN) 69 bit[11] - Specifies DMA request detection type (LVL) 70 bits[12:14] - Specifies DMAACK output mode (AM) 71 bit[15] - Specifies Transfer Mode (TM) 72 73 dma-channels: 74 const: 16 75 76 power-domains: 77 maxItems: 1 78 79 resets: 80 items: 81 - description: Reset for DMA ARESETN reset terminal 82 - description: Reset for DMA RST_ASYNC reset terminal 83 84 reset-names: 85 items: 86 - const: arst 87 - const: rst_async 88 89required: 90 - compatible 91 - reg 92 - interrupts 93 - interrupt-names 94 - '#dma-cells' 95 - dma-channels 96 97allOf: 98 - $ref: dma-controller.yaml# 99 100 - if: 101 not: 102 properties: 103 compatible: 104 contains: 105 enum: 106 - renesas,r7s72100-dmac 107 then: 108 required: 109 - clocks 110 - clock-names 111 - power-domains 112 - resets 113 - reset-names 114 115additionalProperties: false 116 117examples: 118 - | 119 #include <dt-bindings/interrupt-controller/arm-gic.h> 120 #include <dt-bindings/clock/r9a07g044-cpg.h> 121 122 dmac: dma-controller@11820000 { 123 compatible = "renesas,r9a07g044-dmac", 124 "renesas,rz-dmac"; 125 reg = <0x11820000 0x10000>, 126 <0x11830000 0x10000>; 127 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 128 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 129 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 130 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 131 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 132 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 133 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 134 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 135 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 136 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 137 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 138 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 139 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 140 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 141 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 142 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 143 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 144 interrupt-names = "error", 145 "ch0", "ch1", "ch2", "ch3", 146 "ch4", "ch5", "ch6", "ch7", 147 "ch8", "ch9", "ch10", "ch11", 148 "ch12", "ch13", "ch14", "ch15"; 149 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, 150 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; 151 clock-names = "main", "register"; 152 power-domains = <&cpg>; 153 resets = <&cpg R9A07G044_DMAC_ARESETN>, 154 <&cpg R9A07G044_DMAC_RST_ASYNC>; 155 reset-names = "arst", "rst_async"; 156 #dma-cells = <1>; 157 dma-channels = <16>; 158 }; 159