xref: /linux/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml (revision dec1c62e91ba268ab2a6e339d4d7a59287d5eba1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car and RZ/G DMA Controller
8
9maintainers:
10  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
12allOf:
13  - $ref: "dma-controller.yaml#"
14
15properties:
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - renesas,dmac-r8a7742  # RZ/G1H
21              - renesas,dmac-r8a7743  # RZ/G1M
22              - renesas,dmac-r8a7744  # RZ/G1N
23              - renesas,dmac-r8a7745  # RZ/G1E
24              - renesas,dmac-r8a77470 # RZ/G1C
25              - renesas,dmac-r8a774a1 # RZ/G2M
26              - renesas,dmac-r8a774b1 # RZ/G2N
27              - renesas,dmac-r8a774c0 # RZ/G2E
28              - renesas,dmac-r8a774e1 # RZ/G2H
29              - renesas,dmac-r8a7790  # R-Car H2
30              - renesas,dmac-r8a7791  # R-Car M2-W
31              - renesas,dmac-r8a7792  # R-Car V2H
32              - renesas,dmac-r8a7793  # R-Car M2-N
33              - renesas,dmac-r8a7794  # R-Car E2
34              - renesas,dmac-r8a7795  # R-Car H3
35              - renesas,dmac-r8a7796  # R-Car M3-W
36              - renesas,dmac-r8a77961 # R-Car M3-W+
37              - renesas,dmac-r8a77965 # R-Car M3-N
38              - renesas,dmac-r8a77970 # R-Car V3M
39              - renesas,dmac-r8a77980 # R-Car V3H
40              - renesas,dmac-r8a77990 # R-Car E3
41              - renesas,dmac-r8a77995 # R-Car D3
42          - const: renesas,rcar-dmac
43
44      - items:
45          - enum:
46              - renesas,dmac-r8a779a0     # R-Car V3U
47              - renesas,dmac-r8a779f0     # R-Car S4-8
48          - const: renesas,rcar-gen4-dmac # R-Car Gen4
49
50  reg: true
51
52  interrupts:
53    minItems: 9
54    maxItems: 17
55
56  interrupt-names:
57    minItems: 9
58    items:
59      - const: error
60      - pattern: "^ch([0-9]|1[0-5])$"
61      - pattern: "^ch([0-9]|1[0-5])$"
62      - pattern: "^ch([0-9]|1[0-5])$"
63      - pattern: "^ch([0-9]|1[0-5])$"
64      - pattern: "^ch([0-9]|1[0-5])$"
65      - pattern: "^ch([0-9]|1[0-5])$"
66      - pattern: "^ch([0-9]|1[0-5])$"
67      - pattern: "^ch([0-9]|1[0-5])$"
68      - pattern: "^ch([0-9]|1[0-5])$"
69      - pattern: "^ch([0-9]|1[0-5])$"
70      - pattern: "^ch([0-9]|1[0-5])$"
71      - pattern: "^ch([0-9]|1[0-5])$"
72      - pattern: "^ch([0-9]|1[0-5])$"
73      - pattern: "^ch([0-9]|1[0-5])$"
74      - pattern: "^ch([0-9]|1[0-5])$"
75      - pattern: "^ch([0-9]|1[0-5])$"
76
77  clocks:
78    maxItems: 1
79
80  clock-names:
81    items:
82      - const: fck
83
84  '#dma-cells':
85    const: 1
86    description:
87      The cell specifies the MID/RID of the DMAC port connected to
88      the DMA client.
89
90  dma-channels:
91    minimum: 8
92    maximum: 16
93
94  dma-channel-mask: true
95
96  iommus:
97    minItems: 8
98    maxItems: 16
99
100  power-domains:
101    maxItems: 1
102
103  resets:
104    maxItems: 1
105
106required:
107  - compatible
108  - reg
109  - interrupts
110  - interrupt-names
111  - clocks
112  - clock-names
113  - '#dma-cells'
114  - dma-channels
115  - power-domains
116  - resets
117
118if:
119  properties:
120    compatible:
121      contains:
122        enum:
123          - renesas,rcar-gen4-dmac
124then:
125  properties:
126    reg:
127      items:
128        - description: Base register block
129        - description: Channel register block
130else:
131  properties:
132    reg:
133      maxItems: 1
134
135additionalProperties: false
136
137examples:
138  - |
139    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
140    #include <dt-bindings/interrupt-controller/arm-gic.h>
141    #include <dt-bindings/power/r8a7790-sysc.h>
142
143    dmac0: dma-controller@e6700000 {
144        compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
145        reg = <0xe6700000 0x20000>;
146        interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
147                     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
148                     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
149                     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
150                     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
151                     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
152                     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
153                     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
154                     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
155                     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
156                     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
157                     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
158                     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
159                     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
160                     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
161                     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
162        interrupt-names = "error",
163                          "ch0", "ch1", "ch2", "ch3",
164                          "ch4", "ch5", "ch6", "ch7",
165                          "ch8", "ch9", "ch10", "ch11",
166                          "ch12", "ch13", "ch14";
167        clocks = <&cpg CPG_MOD 219>;
168        clock-names = "fck";
169        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
170        resets = <&cpg 219>;
171        #dma-cells = <1>;
172        dma-channels = <15>;
173    };
174