xref: /linux/Documentation/devicetree/bindings/dma/qcom,gpi.yaml (revision fc44ff0ae9f2aa20b64c4e63ab4614156df80240) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies Inc GPI DMA controller
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  QCOM GPI DMA controller provides DMA capabilities for
14  peripheral buses such as I2C, UART, and SPI.
15
16allOf:
17  - $ref: "dma-controller.yaml#"
18
19properties:
20  compatible:
21    enum:
22      - qcom,sc7280-gpi-dma
23      - qcom,sdm845-gpi-dma
24      - qcom,sm8150-gpi-dma
25      - qcom,sm8250-gpi-dma
26      - qcom,sm8350-gpi-dma
27      - qcom,sm8450-gpi-dma
28
29  reg:
30    maxItems: 1
31
32  interrupts:
33    description:
34      Interrupt lines for each GPI instance
35    maxItems: 13
36
37  "#dma-cells":
38    const: 3
39    description: >
40      DMA clients must use the format described in dma.txt, giving a phandle
41      to the DMA controller plus the following 3 integer cells:
42      - channel: if set to 0xffffffff, any available channel will be allocated
43        for the client. Otherwise, the exact channel specified will be used.
44      - seid: serial id of the client as defined in the SoC documentation.
45      - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
46
47  iommus:
48    maxItems: 1
49
50  dma-channels:
51    maximum: 31
52
53  dma-channel-mask:
54    maxItems: 1
55
56required:
57  - compatible
58  - reg
59  - interrupts
60  - "#dma-cells"
61  - iommus
62  - dma-channels
63  - dma-channel-mask
64
65additionalProperties: false
66
67examples:
68  - |
69    #include <dt-bindings/interrupt-controller/arm-gic.h>
70    #include <dt-bindings/dma/qcom-gpi.h>
71    gpi_dma0: dma-controller@800000 {
72        compatible = "qcom,sdm845-gpi-dma";
73        #dma-cells = <3>;
74        reg = <0x00800000 0x60000>;
75        iommus = <&apps_smmu 0x0016 0x0>;
76        dma-channels = <13>;
77        dma-channel-mask = <0xfa>;
78        interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
79                     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
80                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
81                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
82                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
83                     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
84                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
85                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
86                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
87                     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
88                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
89                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
90                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
91    };
92
93...
94