xref: /linux/Documentation/devicetree/bindings/dma/qcom,gpi.yaml (revision 9f2c9170934eace462499ba0bfe042cc72900173) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies Inc GPI DMA controller
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  QCOM GPI DMA controller provides DMA capabilities for
14  peripheral buses such as I2C, UART, and SPI.
15
16allOf:
17  - $ref: "dma-controller.yaml#"
18
19properties:
20  compatible:
21    oneOf:
22      - enum:
23          - qcom,sdm845-gpi-dma
24          - qcom,sm6350-gpi-dma
25      - items:
26          - enum:
27              - qcom,sc7280-gpi-dma
28              - qcom,sm6115-gpi-dma
29              - qcom,sm6375-gpi-dma
30              - qcom,sm8350-gpi-dma
31              - qcom,sm8450-gpi-dma
32          - const: qcom,sm6350-gpi-dma
33      - items:
34          - enum:
35              - qcom,sdm670-gpi-dma
36              - qcom,sm8150-gpi-dma
37              - qcom,sm8250-gpi-dma
38          - const: qcom,sdm845-gpi-dma
39
40  reg:
41    maxItems: 1
42
43  interrupts:
44    description:
45      Interrupt lines for each GPI instance
46    minItems: 1
47    maxItems: 13
48
49  "#dma-cells":
50    const: 3
51    description: >
52      DMA clients must use the format described in dma.txt, giving a phandle
53      to the DMA controller plus the following 3 integer cells:
54      - channel: if set to 0xffffffff, any available channel will be allocated
55        for the client. Otherwise, the exact channel specified will be used.
56      - seid: serial id of the client as defined in the SoC documentation.
57      - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
58
59  iommus:
60    maxItems: 1
61
62  dma-channels:
63    maximum: 31
64
65  dma-channel-mask:
66    maxItems: 1
67
68required:
69  - compatible
70  - reg
71  - interrupts
72  - "#dma-cells"
73  - iommus
74  - dma-channels
75  - dma-channel-mask
76
77additionalProperties: false
78
79examples:
80  - |
81    #include <dt-bindings/interrupt-controller/arm-gic.h>
82    #include <dt-bindings/dma/qcom-gpi.h>
83    gpi_dma0: dma-controller@800000 {
84        compatible = "qcom,sdm845-gpi-dma";
85        #dma-cells = <3>;
86        reg = <0x00800000 0x60000>;
87        iommus = <&apps_smmu 0x0016 0x0>;
88        dma-channels = <13>;
89        dma-channel-mask = <0xfa>;
90        interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
91                     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
92                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
93                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
94                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
95                     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
96                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
97                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
98                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
99                     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
100                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
101                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
102                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
103    };
104
105...
106