xref: /linux/Documentation/devicetree/bindings/dma/qcom,gpi.yaml (revision 2eff01ee2881becc9daaa0d53477ec202136b1f4) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies Inc GPI DMA controller
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  QCOM GPI DMA controller provides DMA capabilities for
14  peripheral buses such as I2C, UART, and SPI.
15
16allOf:
17  - $ref: dma-controller.yaml#
18
19properties:
20  compatible:
21    oneOf:
22      - enum:
23          - qcom,sdm845-gpi-dma
24          - qcom,sm6350-gpi-dma
25      - items:
26          - enum:
27              - qcom,qcm2290-gpi-dma
28              - qcom,qdu1000-gpi-dma
29              - qcom,sar2130p-gpi-dma
30              - qcom,sc7280-gpi-dma
31              - qcom,sdx75-gpi-dma
32              - qcom,sm6115-gpi-dma
33              - qcom,sm6375-gpi-dma
34              - qcom,sm8350-gpi-dma
35              - qcom,sm8450-gpi-dma
36              - qcom,sm8550-gpi-dma
37              - qcom,sm8650-gpi-dma
38              - qcom,x1e80100-gpi-dma
39          - const: qcom,sm6350-gpi-dma
40      - items:
41          - enum:
42              - qcom,sdm670-gpi-dma
43              - qcom,sm6125-gpi-dma
44              - qcom,sm8150-gpi-dma
45              - qcom,sm8250-gpi-dma
46          - const: qcom,sdm845-gpi-dma
47
48  reg:
49    maxItems: 1
50
51  interrupts:
52    description:
53      Interrupt lines for each GPI instance
54    minItems: 1
55    maxItems: 13
56
57  "#dma-cells":
58    const: 3
59    description: >
60      DMA clients must use the format described in dma.txt, giving a phandle
61      to the DMA controller plus the following 3 integer cells:
62      - channel: if set to 0xffffffff, any available channel will be allocated
63        for the client. Otherwise, the exact channel specified will be used.
64      - seid: serial id of the client as defined in the SoC documentation.
65      - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
66
67  iommus:
68    maxItems: 1
69
70  dma-channels:
71    maximum: 31
72
73  dma-channel-mask:
74    maxItems: 1
75
76  dma-coherent: true
77
78required:
79  - compatible
80  - reg
81  - interrupts
82  - "#dma-cells"
83  - iommus
84  - dma-channels
85  - dma-channel-mask
86
87additionalProperties: false
88
89examples:
90  - |
91    #include <dt-bindings/interrupt-controller/arm-gic.h>
92    #include <dt-bindings/dma/qcom-gpi.h>
93    gpi_dma0: dma-controller@800000 {
94        compatible = "qcom,sdm845-gpi-dma";
95        #dma-cells = <3>;
96        reg = <0x00800000 0x60000>;
97        iommus = <&apps_smmu 0x0016 0x0>;
98        dma-channels = <13>;
99        dma-channel-mask = <0xfa>;
100        interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
101                     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
102                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
103                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
104                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
105                     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
106                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
107                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
108                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
109                     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
110                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
111                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
112                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
113    };
114
115...
116