xref: /linux/Documentation/devicetree/bindings/dma/qcom,gpi.yaml (revision 1fd1dc41724319406b0aff221a352a400b0ddfc5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies Inc GPI DMA controller
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  QCOM GPI DMA controller provides DMA capabilities for
14  peripheral buses such as I2C, UART, and SPI.
15
16allOf:
17  - $ref: dma-controller.yaml#
18
19properties:
20  compatible:
21    oneOf:
22      - enum:
23          - qcom,sdm845-gpi-dma
24          - qcom,sm6350-gpi-dma
25      - items:
26          - enum:
27              - qcom,glymur-gpi-dma
28              - qcom,kaanapali-gpi-dma
29              - qcom,milos-gpi-dma
30              - qcom,qcm2290-gpi-dma
31              - qcom,qcs8300-gpi-dma
32              - qcom,qdu1000-gpi-dma
33              - qcom,sa8775p-gpi-dma
34              - qcom,sar2130p-gpi-dma
35              - qcom,sc7280-gpi-dma
36              - qcom,sc8280xp-gpi-dma
37              - qcom,sdx75-gpi-dma
38              - qcom,sm6115-gpi-dma
39              - qcom,sm6375-gpi-dma
40              - qcom,sm8350-gpi-dma
41              - qcom,sm8450-gpi-dma
42              - qcom,sm8550-gpi-dma
43              - qcom,sm8650-gpi-dma
44              - qcom,sm8750-gpi-dma
45              - qcom,x1e80100-gpi-dma
46          - const: qcom,sm6350-gpi-dma
47      - items:
48          - enum:
49              - qcom,qcs615-gpi-dma
50              - qcom,sdm670-gpi-dma
51              - qcom,sm6125-gpi-dma
52              - qcom,sm8150-gpi-dma
53              - qcom,sm8250-gpi-dma
54          - const: qcom,sdm845-gpi-dma
55
56  reg:
57    maxItems: 1
58
59  interrupts:
60    description:
61      Interrupt lines for each GPI instance
62    minItems: 1
63    maxItems: 16
64
65  "#dma-cells":
66    const: 3
67    description: >
68      DMA clients must use the format described in dma.txt, giving a phandle
69      to the DMA controller plus the following 3 integer cells:
70      - channel: if set to 0xffffffff, any available channel will be allocated
71        for the client. Otherwise, the exact channel specified will be used.
72      - seid: serial id of the client as defined in the SoC documentation.
73      - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
74
75  iommus:
76    maxItems: 1
77
78  dma-channels:
79    maximum: 31
80
81  dma-channel-mask:
82    maxItems: 1
83
84  dma-coherent: true
85
86required:
87  - compatible
88  - reg
89  - interrupts
90  - "#dma-cells"
91  - iommus
92  - dma-channels
93  - dma-channel-mask
94
95additionalProperties: false
96
97examples:
98  - |
99    #include <dt-bindings/interrupt-controller/arm-gic.h>
100    #include <dt-bindings/dma/qcom-gpi.h>
101    gpi_dma0: dma-controller@800000 {
102        compatible = "qcom,sdm845-gpi-dma";
103        #dma-cells = <3>;
104        reg = <0x00800000 0x60000>;
105        iommus = <&apps_smmu 0x0016 0x0>;
106        dma-channels = <13>;
107        dma-channel-mask = <0xfa>;
108        interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
109                     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
110                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
111                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
112                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
113                     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
114                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
115                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
116                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
117                     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
118                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
119                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
120                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
121    };
122
123...
124