xref: /linux/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/nvidia,tegra20-apbdma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra APB DMA Controller
8
9description:
10  The NVIDIA Tegra APB DMA controller is a hardware component that
11  enables direct memory access (DMA) on Tegra systems. It facilitates
12  data transfer between I/O devices and main memory without constant
13  CPU intervention.
14
15maintainers:
16  - Jonathan Hunter <jonathanh@nvidia.com>
17
18properties:
19  compatible:
20    oneOf:
21      - const: nvidia,tegra20-apbdma
22      - items:
23          - const: nvidia,tegra30-apbdma
24          - const: nvidia,tegra20-apbdma
25
26  reg:
27    maxItems: 1
28
29  "#dma-cells":
30    const: 1
31
32  clocks:
33    maxItems: 1
34
35  interrupts:
36    description:
37      Should contain all of the per-channel DMA interrupts in
38      ascending order with respect to the DMA channel index.
39    minItems: 1
40    maxItems: 32
41
42  resets:
43    maxItems: 1
44
45  reset-names:
46    const: dma
47
48required:
49  - compatible
50  - reg
51  - "#dma-cells"
52  - clocks
53  - interrupts
54  - resets
55  - reset-names
56
57allOf:
58  - $ref: dma-controller.yaml#
59
60unevaluatedProperties: false
61
62examples:
63  - |
64    #include <dt-bindings/interrupt-controller/arm-gic.h>
65    #include <dt-bindings/reset/tegra186-reset.h>
66    dma-controller@6000a000 {
67        compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
68        reg = <0x6000a000 0x1200>;
69        interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
70                     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
71                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
72                     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
73                     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
74                     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
75                     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
76                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
77                     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
78                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
79                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
80                     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
81                     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
82                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
83                     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
84                     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
85        clocks = <&tegra_car 34>;
86        resets = <&tegra_car 34>;
87        reset-names = "dma";
88        #dma-cells = <1>;
89    };
90...
91