xref: /linux/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml (revision 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek UART APDMA controller
8
9maintainers:
10  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11  - Long Cheng <long.cheng@mediatek.com>
12
13description: |
14  The MediaTek UART APDMA controller provides DMA capabilities
15  for the UART peripheral bus.
16
17allOf:
18  - $ref: dma-controller.yaml#
19
20properties:
21  compatible:
22    oneOf:
23      - items:
24          - enum:
25              - mediatek,mt2712-uart-dma
26              - mediatek,mt6795-uart-dma
27              - mediatek,mt8173-uart-dma
28              - mediatek,mt8183-uart-dma
29              - mediatek,mt8365-uart-dma
30              - mediatek,mt8516-uart-dma
31          - const: mediatek,mt6577-uart-dma
32      - items:
33          - enum:
34              - mediatek,mt7988-uart-dma
35              - mediatek,mt8186-uart-dma
36              - mediatek,mt8188-uart-dma
37              - mediatek,mt8192-uart-dma
38              - mediatek,mt8195-uart-dma
39          - const: mediatek,mt6835-uart-dma
40      - items:
41          - enum:
42              - mediatek,mt6991-uart-dma
43              - mediatek,mt8189-uart-dma
44              - mediatek,mt8196-uart-dma
45          - const: mediatek,mt6985-uart-dma
46      - enum:
47          - mediatek,mt6577-uart-dma
48          - mediatek,mt6795-uart-dma
49          - mediatek,mt6835-uart-dma
50          - mediatek,mt6985-uart-dma
51
52  reg:
53    minItems: 1
54    maxItems: 16
55
56  interrupts:
57    description: |
58      TX, RX interrupt lines for each UART APDMA channel
59    minItems: 1
60    maxItems: 16
61
62  clocks:
63    description: Must contain one entry for the APDMA main clock
64    maxItems: 1
65
66  clock-names:
67    const: apdma
68
69  "#dma-cells":
70    const: 1
71    description: |
72      The first cell specifies the UART APDMA channel number
73
74  dma-requests:
75    description: |
76      Number of virtual channels of the UART APDMA controller
77    maximum: 16
78
79  mediatek,dma-33bits:
80    type: boolean
81    deprecated: true
82    description: Enable 33-bits UART APDMA support
83
84required:
85  - compatible
86  - reg
87  - interrupts
88
89additionalProperties: false
90
91if:
92  not:
93    required:
94      - dma-requests
95then:
96  properties:
97    interrupts:
98      maxItems: 8
99    reg:
100      maxItems: 8
101
102examples:
103  - |
104    #include <dt-bindings/interrupt-controller/arm-gic.h>
105    #include <dt-bindings/clock/mt2712-clk.h>
106    soc {
107        #address-cells = <2>;
108        #size-cells = <2>;
109
110        apdma: dma-controller@11000400 {
111            compatible = "mediatek,mt2712-uart-dma",
112                         "mediatek,mt6577-uart-dma";
113            reg = <0 0x11000400 0 0x80>,
114                  <0 0x11000480 0 0x80>,
115                  <0 0x11000500 0 0x80>,
116                  <0 0x11000580 0 0x80>,
117                  <0 0x11000600 0 0x80>,
118                  <0 0x11000680 0 0x80>,
119                  <0 0x11000700 0 0x80>,
120                  <0 0x11000780 0 0x80>,
121                  <0 0x11000800 0 0x80>,
122                  <0 0x11000880 0 0x80>,
123                  <0 0x11000900 0 0x80>,
124                  <0 0x11000980 0 0x80>;
125            interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
126                         <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
127                         <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
128                         <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
129                         <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
130                         <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
131                         <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
132                         <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
133                         <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
134                         <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
135                         <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
136                         <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
137            dma-requests = <12>;
138            clocks = <&pericfg CLK_PERI_AP_DMA>;
139            clock-names = "apdma";
140            mediatek,dma-33bits;
141            #dma-cells = <1>;
142        };
143    };
144
145...
146