xref: /linux/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml (revision 1fd1dc41724319406b0aff221a352a400b0ddfc5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek UART APDMA controller
8
9maintainers:
10  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11  - Long Cheng <long.cheng@mediatek.com>
12
13description: |
14  The MediaTek UART APDMA controller provides DMA capabilities
15  for the UART peripheral bus.
16
17allOf:
18  - $ref: dma-controller.yaml#
19
20properties:
21  compatible:
22    oneOf:
23      - items:
24          - enum:
25              - mediatek,mt2712-uart-dma
26              - mediatek,mt6795-uart-dma
27              - mediatek,mt8173-uart-dma
28              - mediatek,mt8183-uart-dma
29              - mediatek,mt8365-uart-dma
30              - mediatek,mt8516-uart-dma
31          - const: mediatek,mt6577-uart-dma
32      - items:
33          - enum:
34              - mediatek,mt7988-uart-dma
35              - mediatek,mt8186-uart-dma
36              - mediatek,mt8188-uart-dma
37              - mediatek,mt8192-uart-dma
38              - mediatek,mt8195-uart-dma
39          - const: mediatek,mt6835-uart-dma
40      - items:
41          - enum:
42              - mediatek,mt6991-uart-dma
43              - mediatek,mt8196-uart-dma
44          - const: mediatek,mt6985-uart-dma
45      - enum:
46          - mediatek,mt6577-uart-dma
47          - mediatek,mt6795-uart-dma
48          - mediatek,mt6835-uart-dma
49          - mediatek,mt6985-uart-dma
50
51  reg:
52    minItems: 1
53    maxItems: 16
54
55  interrupts:
56    description: |
57      TX, RX interrupt lines for each UART APDMA channel
58    minItems: 1
59    maxItems: 16
60
61  clocks:
62    description: Must contain one entry for the APDMA main clock
63    maxItems: 1
64
65  clock-names:
66    const: apdma
67
68  "#dma-cells":
69    const: 1
70    description: |
71      The first cell specifies the UART APDMA channel number
72
73  dma-requests:
74    description: |
75      Number of virtual channels of the UART APDMA controller
76    maximum: 16
77
78  mediatek,dma-33bits:
79    type: boolean
80    deprecated: true
81    description: Enable 33-bits UART APDMA support
82
83required:
84  - compatible
85  - reg
86  - interrupts
87
88additionalProperties: false
89
90if:
91  not:
92    required:
93      - dma-requests
94then:
95  properties:
96    interrupts:
97      maxItems: 8
98    reg:
99      maxItems: 8
100
101examples:
102  - |
103    #include <dt-bindings/interrupt-controller/arm-gic.h>
104    #include <dt-bindings/clock/mt2712-clk.h>
105    soc {
106        #address-cells = <2>;
107        #size-cells = <2>;
108
109        apdma: dma-controller@11000400 {
110            compatible = "mediatek,mt2712-uart-dma",
111                         "mediatek,mt6577-uart-dma";
112            reg = <0 0x11000400 0 0x80>,
113                  <0 0x11000480 0 0x80>,
114                  <0 0x11000500 0 0x80>,
115                  <0 0x11000580 0 0x80>,
116                  <0 0x11000600 0 0x80>,
117                  <0 0x11000680 0 0x80>,
118                  <0 0x11000700 0 0x80>,
119                  <0 0x11000780 0 0x80>,
120                  <0 0x11000800 0 0x80>,
121                  <0 0x11000880 0 0x80>,
122                  <0 0x11000900 0 0x80>,
123                  <0 0x11000980 0 0x80>;
124            interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
125                         <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
126                         <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
127                         <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
128                         <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
129                         <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
130                         <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
131                         <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
132                         <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
133                         <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
134                         <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
135                         <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
136            dma-requests = <12>;
137            clocks = <&pericfg CLK_PERI_AP_DMA>;
138            clock-names = "apdma";
139            mediatek,dma-33bits;
140            #dma-cells = <1>;
141        };
142    };
143
144...
145