xref: /linux/Documentation/devicetree/bindings/dma/mediatek,mt7622-hsdma.yaml (revision b228ab57e51b62663a80ca820c87ba2650583f08) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/mediatek,mt7622-hsdma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek High-Speed DMA Controller
8
9maintainers:
10  - Sean Wang <sean.wang@mediatek.com>
11
12allOf:
13  - $ref: dma-controller.yaml#
14
15properties:
16  compatible:
17    enum:
18      - mediatek,mt7622-hsdma
19      - mediatek,mt7623-hsdma
20
21  reg:
22    maxItems: 1
23
24  interrupts:
25    maxItems: 1
26
27  clocks:
28    maxItems: 1
29
30  clock-names:
31    const: hsdma
32
33  power-domains:
34    maxItems: 1
35
36  "#dma-cells":
37    description: Channel number
38    const: 1
39
40required:
41  - reg
42  - interrupts
43  - clocks
44  - clock-names
45  - power-domains
46
47unevaluatedProperties: false
48
49examples:
50  - |
51    #include <dt-bindings/clock/mt2701-clk.h>
52    #include <dt-bindings/interrupt-controller/arm-gic.h>
53    #include <dt-bindings/power/mt2701-power.h>
54
55    dma-controller@1b007000 {
56        compatible = "mediatek,mt7623-hsdma";
57        reg = <0x1b007000 0x1000>;
58        interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
59        clocks = <&ethsys CLK_ETHSYS_HSDMA>;
60        clock-names = "hsdma";
61        power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
62        #dma-cells = <1>;
63    };
64