xref: /linux/Documentation/devicetree/bindings/dma/fsl,edma.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale enhanced Direct Memory Access(eDMA) Controller
8
9description: |
10  The eDMA channels have multiplex capability by programmable
11  memory-mapped registers. channels are split into two groups, called
12  DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
13  by any channel of certain group, DMAMUX0 or DMAMUX1, but not both.
14
15maintainers:
16  - Peng Fan <peng.fan@nxp.com>
17
18properties:
19  compatible:
20    oneOf:
21      - enum:
22          - fsl,vf610-edma
23          - fsl,imx7ulp-edma
24          - fsl,imx8qm-edma
25          - fsl,imx8ulp-edma
26          - fsl,imx93-edma3
27          - fsl,imx93-edma4
28          - fsl,imx95-edma5
29          - nxp,s32g2-edma
30      - items:
31          - enum:
32              - fsl,imx94-edma3
33          - const: fsl,imx93-edma3
34      - items:
35          - enum:
36              - fsl,imx94-edma5
37          - const: fsl,imx95-edma5
38      - items:
39          - const: fsl,ls1028a-edma
40          - const: fsl,vf610-edma
41      - items:
42          - const: nxp,s32g3-edma
43          - const: nxp,s32g2-edma
44
45  reg:
46    minItems: 1
47    maxItems: 3
48
49  interrupts:
50    minItems: 1
51    maxItems: 65
52
53  interrupt-names:
54    minItems: 1
55    maxItems: 65
56
57  "#dma-cells":
58    description: |
59      Specifies the number of cells needed to encode an DMA channel.
60
61      Encode for cells number 2:
62        cell 0: index of dma channel mux instance.
63        cell 1: peripheral dma request id.
64
65      Encode for cells number 3:
66        cell 0: peripheral dma request id.
67        cell 1: dma channel priority.
68        cell 2: bitmask, defined at include/dt-bindings/dma/fsl-edma.h
69    enum:
70      - 2
71      - 3
72
73  dma-channels:
74    minimum: 1
75    maximum: 64
76
77  clocks:
78    minItems: 1
79    maxItems: 33
80
81  clock-names:
82    minItems: 1
83    maxItems: 33
84
85  power-domains:
86    description:
87      The number of power domains matches the number of channels, arranged
88      in ascending order according to their associated DMA channels.
89    minItems: 1
90    maxItems: 64
91
92  big-endian:
93    description: |
94      If present registers and hardware scatter/gather descriptors of the
95      eDMA are implemented in big endian mode, otherwise in little mode.
96    type: boolean
97
98required:
99  - "#dma-cells"
100  - compatible
101  - reg
102  - interrupts
103  - dma-channels
104
105allOf:
106  - $ref: dma-controller.yaml#
107  - if:
108      properties:
109        compatible:
110          contains:
111            enum:
112              - fsl,imx8qm-edma
113              - fsl,imx93-edma3
114              - fsl,imx93-edma4
115              - fsl,imx95-edma5
116    then:
117      properties:
118        "#dma-cells":
119          const: 3
120        # It is not necessary to write the interrupt name for each channel.
121        # instead, you can simply maintain the sequential IRQ numbers as
122        # defined for the DMA channels.
123        interrupt-names: false
124        clock-names:
125          items:
126            - const: dma
127        clocks:
128          maxItems: 1
129
130  - if:
131      properties:
132        compatible:
133          contains:
134            const: fsl,vf610-edma
135    then:
136      properties:
137        clocks:
138          minItems: 2
139          maxItems: 2
140        clock-names:
141          items:
142            - const: dmamux0
143            - const: dmamux1
144        interrupts:
145          minItems: 2
146          maxItems: 2
147        interrupt-names:
148          items:
149            - const: edma-tx
150            - const: edma-err
151        reg:
152          minItems: 2
153          maxItems: 3
154        "#dma-cells":
155          const: 2
156        dma-channels:
157          const: 32
158
159  - if:
160      properties:
161        compatible:
162          contains:
163            const: fsl,imx7ulp-edma
164    then:
165      properties:
166        clock:
167          minItems: 2
168          maxItems: 2
169        clock-names:
170          items:
171            - const: dma
172            - const: dmamux0
173        interrupts:
174          minItems: 2
175          maxItems: 17
176        reg:
177          minItems: 2
178          maxItems: 2
179        "#dma-cells":
180          const: 2
181        dma-channels:
182          const: 32
183
184  - if:
185      properties:
186        compatible:
187          contains:
188            const: fsl,imx8ulp-edma
189    then:
190      properties:
191        clocks:
192          minItems: 33
193        clock-names:
194          minItems: 33
195          items:
196            oneOf:
197              - const: dma
198              - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$"
199
200        interrupt-names: false
201        interrupts:
202          minItems: 32
203        "#dma-cells":
204          const: 3
205
206  - if:
207      properties:
208        compatible:
209          contains:
210            enum:
211              - fsl,vf610-edma
212              - fsl,imx7ulp-edma
213              - fsl,imx93-edma3
214              - fsl,imx93-edma4
215              - fsl,imx95-edma5
216              - fsl,imx8ulp-edma
217              - fsl,ls1028a-edma
218    then:
219      required:
220        - clocks
221
222  - if:
223      properties:
224        compatible:
225          contains:
226            enum:
227              - fsl,imx8qm-adma
228              - fsl,imx8qm-edma
229    then:
230      required:
231        - power-domains
232    else:
233      properties:
234        power-domains: false
235
236  - if:
237      properties:
238        compatible:
239          contains:
240            const: nxp,s32g2-edma
241    then:
242      properties:
243        clocks:
244          minItems: 2
245          maxItems: 2
246        clock-names:
247          items:
248            - const: dmamux0
249            - const: dmamux1
250        interrupts:
251          minItems: 3
252          maxItems: 3
253        interrupt-names:
254          items:
255            - const: tx-0-15
256            - const: tx-16-31
257            - const: err
258        reg:
259          minItems: 3
260          maxItems: 3
261        "#dma-cells":
262          const: 2
263        dma-channels:
264          const: 32
265
266unevaluatedProperties: false
267
268examples:
269  - |
270    #include <dt-bindings/interrupt-controller/arm-gic.h>
271    #include <dt-bindings/clock/vf610-clock.h>
272
273    edma0: dma-controller@40018000 {
274      #dma-cells = <2>;
275      compatible = "fsl,vf610-edma";
276      reg = <0x40018000 0x2000>,
277            <0x40024000 0x1000>,
278            <0x40025000 0x1000>;
279      interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
280                   <0 9 IRQ_TYPE_LEVEL_HIGH>;
281      interrupt-names = "edma-tx", "edma-err";
282      dma-channels = <32>;
283      clock-names = "dmamux0", "dmamux1";
284      clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>;
285    };
286
287  - |
288    #include <dt-bindings/interrupt-controller/arm-gic.h>
289    #include <dt-bindings/clock/imx7ulp-clock.h>
290
291    edma1: dma-controller@40080000 {
292      #dma-cells = <2>;
293      compatible = "fsl,imx7ulp-edma";
294      reg = <0x40080000 0x2000>,
295            <0x40210000 0x1000>;
296      dma-channels = <32>;
297      interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
298                   <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
299                   <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
300                   <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
301                   <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
302                   <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
303                   <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
304                   <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
305                   <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
306                   <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
307                   <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
308                   <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
309                   <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
310                   <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
311                   <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
312                   <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
313                   /* last is eDMA2-ERR interrupt */
314                   <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
315       clock-names = "dma", "dmamux0";
316       clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
317    };
318
319  - |
320    #include <dt-bindings/interrupt-controller/arm-gic.h>
321    #include <dt-bindings/firmware/imx/rsrc.h>
322
323    dma-controller@5a9f0000 {
324      compatible = "fsl,imx8qm-edma";
325      reg = <0x5a9f0000 0x90000>;
326      #dma-cells = <3>;
327      dma-channels = <8>;
328      interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
329                   <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
330                   <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
331                   <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
332                   <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
333                   <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
334                   <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
335                   <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
336      power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
337                      <&pd IMX_SC_R_DMA_3_CH1>,
338                      <&pd IMX_SC_R_DMA_3_CH2>,
339                      <&pd IMX_SC_R_DMA_3_CH3>,
340                      <&pd IMX_SC_R_DMA_3_CH4>,
341                      <&pd IMX_SC_R_DMA_3_CH5>,
342                      <&pd IMX_SC_R_DMA_3_CH6>,
343                      <&pd IMX_SC_R_DMA_3_CH7>;
344    };
345