1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/dma/fsl,edma.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale enhanced Direct Memory Access(eDMA) Controller 8 9description: | 10 The eDMA channels have multiplex capability by programmable 11 memory-mapped registers. channels are split into two groups, called 12 DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed 13 by any channel of certain group, DMAMUX0 or DMAMUX1, but not both. 14 15maintainers: 16 - Peng Fan <peng.fan@nxp.com> 17 18properties: 19 compatible: 20 oneOf: 21 - enum: 22 - fsl,vf610-edma 23 - fsl,imx7ulp-edma 24 - fsl,imx8qm-adma 25 - fsl,imx8qm-edma 26 - fsl,imx93-edma3 27 - fsl,imx93-edma4 28 - items: 29 - const: fsl,ls1028a-edma 30 - const: fsl,vf610-edma 31 32 reg: 33 minItems: 1 34 maxItems: 3 35 36 interrupts: 37 minItems: 1 38 maxItems: 64 39 40 interrupt-names: 41 minItems: 1 42 maxItems: 64 43 44 "#dma-cells": 45 enum: 46 - 2 47 - 3 48 49 dma-channels: 50 minItems: 1 51 maxItems: 64 52 53 clocks: 54 minItems: 1 55 maxItems: 2 56 57 clock-names: 58 minItems: 1 59 maxItems: 2 60 61 big-endian: 62 description: | 63 If present registers and hardware scatter/gather descriptors of the 64 eDMA are implemented in big endian mode, otherwise in little mode. 65 type: boolean 66 67required: 68 - "#dma-cells" 69 - compatible 70 - reg 71 - interrupts 72 - clocks 73 - dma-channels 74 75allOf: 76 - $ref: dma-controller.yaml# 77 - if: 78 properties: 79 compatible: 80 contains: 81 enum: 82 - fsl,imx8qm-adma 83 - fsl,imx8qm-edma 84 - fsl,imx93-edma3 85 - fsl,imx93-edma4 86 then: 87 properties: 88 "#dma-cells": 89 const: 3 90 # It is not necessary to write the interrupt name for each channel. 91 # instead, you can simply maintain the sequential IRQ numbers as 92 # defined for the DMA channels. 93 interrupt-names: false 94 clock-names: 95 items: 96 - const: dma 97 clocks: 98 maxItems: 1 99 100 - if: 101 properties: 102 compatible: 103 contains: 104 const: fsl,vf610-edma 105 then: 106 properties: 107 clocks: 108 minItems: 2 109 clock-names: 110 items: 111 - const: dmamux0 112 - const: dmamux1 113 interrupts: 114 minItems: 2 115 maxItems: 2 116 interrupt-names: 117 items: 118 - const: edma-tx 119 - const: edma-err 120 reg: 121 minItems: 2 122 maxItems: 3 123 "#dma-cells": 124 const: 2 125 dma-channels: 126 const: 32 127 128 - if: 129 properties: 130 compatible: 131 contains: 132 const: fsl,imx7ulp-edma 133 then: 134 properties: 135 clock: 136 minItems: 2 137 clock-names: 138 items: 139 - const: dma 140 - const: dmamux0 141 interrupts: 142 minItems: 2 143 maxItems: 17 144 reg: 145 minItems: 2 146 maxItems: 2 147 "#dma-cells": 148 const: 2 149 dma-channels: 150 const: 32 151 152unevaluatedProperties: false 153 154examples: 155 - | 156 #include <dt-bindings/interrupt-controller/arm-gic.h> 157 #include <dt-bindings/clock/vf610-clock.h> 158 159 edma0: dma-controller@40018000 { 160 #dma-cells = <2>; 161 compatible = "fsl,vf610-edma"; 162 reg = <0x40018000 0x2000>, 163 <0x40024000 0x1000>, 164 <0x40025000 0x1000>; 165 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, 166 <0 9 IRQ_TYPE_LEVEL_HIGH>; 167 interrupt-names = "edma-tx", "edma-err"; 168 dma-channels = <32>; 169 clock-names = "dmamux0", "dmamux1"; 170 clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>; 171 }; 172 173 - | 174 #include <dt-bindings/interrupt-controller/arm-gic.h> 175 #include <dt-bindings/clock/imx7ulp-clock.h> 176 177 edma1: dma-controller@40080000 { 178 #dma-cells = <2>; 179 compatible = "fsl,imx7ulp-edma"; 180 reg = <0x40080000 0x2000>, 181 <0x40210000 0x1000>; 182 dma-channels = <32>; 183 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 199 /* last is eDMA2-ERR interrupt */ 200 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 201 clock-names = "dma", "dmamux0"; 202 clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; 203 }; 204 205 - | 206 #include <dt-bindings/interrupt-controller/arm-gic.h> 207 #include <dt-bindings/clock/imx93-clock.h> 208 209 dma-controller@44000000 { 210 compatible = "fsl,imx93-edma3"; 211 reg = <0x44000000 0x200000>; 212 #dma-cells = <3>; 213 dma-channels = <31>; 214 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&clk IMX93_CLK_EDMA1_GATE>; 246 clock-names = "dma"; 247 }; 248