1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/dma/fsl,edma.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale enhanced Direct Memory Access(eDMA) Controller 8 9description: | 10 The eDMA channels have multiplex capability by programmable 11 memory-mapped registers. channels are split into two groups, called 12 DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed 13 by any channel of certain group, DMAMUX0 or DMAMUX1, but not both. 14 15maintainers: 16 - Peng Fan <peng.fan@nxp.com> 17 18properties: 19 compatible: 20 oneOf: 21 - enum: 22 - fsl,vf610-edma 23 - fsl,imx7ulp-edma 24 - fsl,imx8qm-adma 25 - fsl,imx8qm-edma 26 - fsl,imx93-edma3 27 - fsl,imx93-edma4 28 - fsl,imx95-edma5 29 - items: 30 - const: fsl,ls1028a-edma 31 - const: fsl,vf610-edma 32 33 reg: 34 minItems: 1 35 maxItems: 3 36 37 interrupts: 38 minItems: 1 39 maxItems: 64 40 41 interrupt-names: 42 minItems: 1 43 maxItems: 64 44 45 "#dma-cells": 46 enum: 47 - 2 48 - 3 49 50 dma-channels: 51 minItems: 1 52 maxItems: 64 53 54 clocks: 55 minItems: 1 56 maxItems: 2 57 58 clock-names: 59 minItems: 1 60 maxItems: 2 61 62 big-endian: 63 description: | 64 If present registers and hardware scatter/gather descriptors of the 65 eDMA are implemented in big endian mode, otherwise in little mode. 66 type: boolean 67 68required: 69 - "#dma-cells" 70 - compatible 71 - reg 72 - interrupts 73 - clocks 74 - dma-channels 75 76allOf: 77 - $ref: dma-controller.yaml# 78 - if: 79 properties: 80 compatible: 81 contains: 82 enum: 83 - fsl,imx8qm-adma 84 - fsl,imx8qm-edma 85 - fsl,imx93-edma3 86 - fsl,imx93-edma4 87 - fsl,imx95-edma5 88 then: 89 properties: 90 "#dma-cells": 91 const: 3 92 # It is not necessary to write the interrupt name for each channel. 93 # instead, you can simply maintain the sequential IRQ numbers as 94 # defined for the DMA channels. 95 interrupt-names: false 96 clock-names: 97 items: 98 - const: dma 99 clocks: 100 maxItems: 1 101 102 - if: 103 properties: 104 compatible: 105 contains: 106 const: fsl,vf610-edma 107 then: 108 properties: 109 clocks: 110 minItems: 2 111 clock-names: 112 items: 113 - const: dmamux0 114 - const: dmamux1 115 interrupts: 116 minItems: 2 117 maxItems: 2 118 interrupt-names: 119 items: 120 - const: edma-tx 121 - const: edma-err 122 reg: 123 minItems: 2 124 maxItems: 3 125 "#dma-cells": 126 const: 2 127 dma-channels: 128 const: 32 129 130 - if: 131 properties: 132 compatible: 133 contains: 134 const: fsl,imx7ulp-edma 135 then: 136 properties: 137 clock: 138 minItems: 2 139 clock-names: 140 items: 141 - const: dma 142 - const: dmamux0 143 interrupts: 144 minItems: 2 145 maxItems: 17 146 reg: 147 minItems: 2 148 maxItems: 2 149 "#dma-cells": 150 const: 2 151 dma-channels: 152 const: 32 153 154unevaluatedProperties: false 155 156examples: 157 - | 158 #include <dt-bindings/interrupt-controller/arm-gic.h> 159 #include <dt-bindings/clock/vf610-clock.h> 160 161 edma0: dma-controller@40018000 { 162 #dma-cells = <2>; 163 compatible = "fsl,vf610-edma"; 164 reg = <0x40018000 0x2000>, 165 <0x40024000 0x1000>, 166 <0x40025000 0x1000>; 167 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, 168 <0 9 IRQ_TYPE_LEVEL_HIGH>; 169 interrupt-names = "edma-tx", "edma-err"; 170 dma-channels = <32>; 171 clock-names = "dmamux0", "dmamux1"; 172 clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>; 173 }; 174 175 - | 176 #include <dt-bindings/interrupt-controller/arm-gic.h> 177 #include <dt-bindings/clock/imx7ulp-clock.h> 178 179 edma1: dma-controller@40080000 { 180 #dma-cells = <2>; 181 compatible = "fsl,imx7ulp-edma"; 182 reg = <0x40080000 0x2000>, 183 <0x40210000 0x1000>; 184 dma-channels = <32>; 185 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 201 /* last is eDMA2-ERR interrupt */ 202 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 203 clock-names = "dma", "dmamux0"; 204 clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; 205 }; 206 207 - | 208 #include <dt-bindings/interrupt-controller/arm-gic.h> 209 #include <dt-bindings/clock/imx93-clock.h> 210 211 dma-controller@44000000 { 212 compatible = "fsl,imx93-edma3"; 213 reg = <0x44000000 0x200000>; 214 #dma-cells = <3>; 215 dma-channels = <31>; 216 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&clk IMX93_CLK_EDMA1_GATE>; 248 clock-names = "dma"; 249 }; 250