1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/dma/fsl,edma.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale enhanced Direct Memory Access(eDMA) Controller 8 9description: | 10 The eDMA channels have multiplex capability by programmable 11 memory-mapped registers. channels are split into two groups, called 12 DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed 13 by any channel of certain group, DMAMUX0 or DMAMUX1, but not both. 14 15 This binding has an inverted dma-channel-mask definition compared to 16 the common DMA binding for historical reasons. 17 18maintainers: 19 - Peng Fan <peng.fan@nxp.com> 20 21properties: 22 compatible: 23 oneOf: 24 - enum: 25 - fsl,vf610-edma 26 - fsl,imx7ulp-edma 27 - fsl,imx8qm-edma 28 - fsl,imx8ulp-edma 29 - fsl,imx93-edma3 30 - fsl,imx93-edma4 31 - fsl,imx95-edma5 32 - nxp,s32g2-edma 33 - items: 34 - enum: 35 - fsl,imx94-edma3 36 - const: fsl,imx93-edma3 37 - items: 38 - enum: 39 - fsl,imx94-edma5 40 - const: fsl,imx95-edma5 41 - items: 42 - const: fsl,ls1028a-edma 43 - const: fsl,vf610-edma 44 - items: 45 - const: nxp,s32g3-edma 46 - const: nxp,s32g2-edma 47 48 reg: 49 minItems: 1 50 maxItems: 3 51 52 interrupts: 53 minItems: 1 54 maxItems: 65 55 56 interrupt-names: 57 minItems: 1 58 maxItems: 65 59 60 "#dma-cells": 61 description: | 62 Specifies the number of cells needed to encode an DMA channel. 63 64 Encode for cells number 2: 65 cell 0: index of dma channel mux instance. 66 cell 1: peripheral dma request id. 67 68 Encode for cells number 3: 69 cell 0: peripheral dma request id. 70 cell 1: dma channel priority. 71 cell 2: bitmask, defined at include/dt-bindings/dma/fsl-edma.h 72 enum: 73 - 2 74 - 3 75 76 dma-channels: 77 minimum: 1 78 maximum: 64 79 80 clocks: 81 minItems: 1 82 maxItems: 33 83 84 clock-names: 85 minItems: 1 86 maxItems: 33 87 88 power-domains: 89 description: 90 The number of power domains matches the number of channels, arranged 91 in ascending order according to their associated DMA channels. 92 minItems: 1 93 maxItems: 64 94 95 big-endian: 96 description: | 97 If present registers and hardware scatter/gather descriptors of the 98 eDMA are implemented in big endian mode, otherwise in little mode. 99 type: boolean 100 101 dma-channel-mask: 102 description: | 103 Bitmask of available DMA channels (inverted definition). 104 Bit semantics: 0 means channel available, 1 means channel unavailable 105 default: 0 106 107required: 108 - "#dma-cells" 109 - compatible 110 - reg 111 - interrupts 112 - dma-channels 113 114allOf: 115 - $ref: dma-controller.yaml# 116 - if: 117 properties: 118 compatible: 119 contains: 120 enum: 121 - fsl,imx8qm-edma 122 - fsl,imx93-edma3 123 - fsl,imx93-edma4 124 - fsl,imx95-edma5 125 then: 126 properties: 127 "#dma-cells": 128 const: 3 129 # It is not necessary to write the interrupt name for each channel. 130 # instead, you can simply maintain the sequential IRQ numbers as 131 # defined for the DMA channels. 132 interrupt-names: false 133 clock-names: 134 items: 135 - const: dma 136 clocks: 137 maxItems: 1 138 139 - if: 140 properties: 141 compatible: 142 contains: 143 const: fsl,vf610-edma 144 then: 145 properties: 146 clocks: 147 minItems: 2 148 maxItems: 2 149 clock-names: 150 items: 151 - const: dmamux0 152 - const: dmamux1 153 interrupts: 154 minItems: 2 155 maxItems: 2 156 interrupt-names: 157 items: 158 - const: edma-tx 159 - const: edma-err 160 reg: 161 minItems: 2 162 maxItems: 3 163 "#dma-cells": 164 const: 2 165 dma-channels: 166 const: 32 167 168 - if: 169 properties: 170 compatible: 171 contains: 172 const: fsl,imx7ulp-edma 173 then: 174 properties: 175 clock: 176 minItems: 2 177 maxItems: 2 178 clock-names: 179 items: 180 - const: dma 181 - const: dmamux0 182 interrupts: 183 minItems: 2 184 maxItems: 17 185 reg: 186 minItems: 2 187 maxItems: 2 188 "#dma-cells": 189 const: 2 190 dma-channels: 191 const: 32 192 193 - if: 194 properties: 195 compatible: 196 contains: 197 const: fsl,imx8ulp-edma 198 then: 199 properties: 200 clocks: 201 minItems: 33 202 clock-names: 203 minItems: 33 204 items: 205 oneOf: 206 - const: dma 207 - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$" 208 209 interrupt-names: false 210 interrupts: 211 minItems: 32 212 "#dma-cells": 213 const: 3 214 215 - if: 216 properties: 217 compatible: 218 contains: 219 enum: 220 - fsl,vf610-edma 221 - fsl,imx7ulp-edma 222 - fsl,imx93-edma3 223 - fsl,imx93-edma4 224 - fsl,imx95-edma5 225 - fsl,imx8ulp-edma 226 - fsl,ls1028a-edma 227 then: 228 required: 229 - clocks 230 231 - if: 232 properties: 233 compatible: 234 contains: 235 enum: 236 - fsl,imx8qm-adma 237 - fsl,imx8qm-edma 238 then: 239 required: 240 - power-domains 241 else: 242 properties: 243 power-domains: false 244 245 - if: 246 properties: 247 compatible: 248 contains: 249 const: nxp,s32g2-edma 250 then: 251 properties: 252 clocks: 253 minItems: 2 254 maxItems: 2 255 clock-names: 256 items: 257 - const: dmamux0 258 - const: dmamux1 259 interrupts: 260 minItems: 3 261 maxItems: 3 262 interrupt-names: 263 items: 264 - const: tx-0-15 265 - const: tx-16-31 266 - const: err 267 reg: 268 minItems: 3 269 maxItems: 3 270 "#dma-cells": 271 const: 2 272 dma-channels: 273 const: 32 274 275unevaluatedProperties: false 276 277examples: 278 - | 279 #include <dt-bindings/interrupt-controller/arm-gic.h> 280 #include <dt-bindings/clock/vf610-clock.h> 281 282 edma0: dma-controller@40018000 { 283 #dma-cells = <2>; 284 compatible = "fsl,vf610-edma"; 285 reg = <0x40018000 0x2000>, 286 <0x40024000 0x1000>, 287 <0x40025000 0x1000>; 288 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, 289 <0 9 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "edma-tx", "edma-err"; 291 dma-channels = <32>; 292 clock-names = "dmamux0", "dmamux1"; 293 clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>; 294 }; 295 296 - | 297 #include <dt-bindings/interrupt-controller/arm-gic.h> 298 #include <dt-bindings/clock/imx7ulp-clock.h> 299 300 edma1: dma-controller@40080000 { 301 #dma-cells = <2>; 302 compatible = "fsl,imx7ulp-edma"; 303 reg = <0x40080000 0x2000>, 304 <0x40210000 0x1000>; 305 dma-channels = <32>; 306 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 322 /* last is eDMA2-ERR interrupt */ 323 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 324 clock-names = "dma", "dmamux0"; 325 clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; 326 }; 327 328 - | 329 #include <dt-bindings/interrupt-controller/arm-gic.h> 330 #include <dt-bindings/firmware/imx/rsrc.h> 331 332 dma-controller@5a9f0000 { 333 compatible = "fsl,imx8qm-edma"; 334 reg = <0x5a9f0000 0x90000>; 335 #dma-cells = <3>; 336 dma-channels = <8>; 337 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; 345 power-domains = <&pd IMX_SC_R_DMA_3_CH0>, 346 <&pd IMX_SC_R_DMA_3_CH1>, 347 <&pd IMX_SC_R_DMA_3_CH2>, 348 <&pd IMX_SC_R_DMA_3_CH3>, 349 <&pd IMX_SC_R_DMA_3_CH4>, 350 <&pd IMX_SC_R_DMA_3_CH5>, 351 <&pd IMX_SC_R_DMA_3_CH6>, 352 <&pd IMX_SC_R_DMA_3_CH7>; 353 }; 354