1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/dma/atmel,sama5d4-dma.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Microchip AT91 Extensible Direct Memory Access Controller 8 9maintainers: 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 - Charan Pedumuru <charan.pedumuru@microchip.com> 12 13description: 14 The DMA Controller (XDMAC) is a AHB-protocol central direct memory access 15 controller. It performs peripheral data transfer and memory move operations 16 over one or two bus ports through the unidirectional communication 17 channel. Each channel is fully programmable and provides both peripheral 18 or memory-to-memory transfers. The channel features are configurable at 19 implementation. 20 21allOf: 22 - $ref: dma-controller.yaml# 23 24properties: 25 compatible: 26 oneOf: 27 - enum: 28 - atmel,sama5d4-dma 29 - microchip,sama7g5-dma 30 - items: 31 - enum: 32 - microchip,sam9x60-dma 33 - microchip,sam9x7-dma 34 - const: atmel,sama5d4-dma 35 - items: 36 - const: microchip,sama7d65-dma 37 - const: microchip,sama7g5-dma 38 39 "#dma-cells": 40 description: | 41 Represents the number of integer cells in the `dmas` property of client 42 devices. The single cell specifies the channel configuration register: 43 - bit 13: SIF (Source Interface Identifier) for memory interface. 44 - bit 14: DIF (Destination Interface Identifier) for peripheral interface. 45 - bit 30-24: PERID (Peripheral Identifier). 46 const: 1 47 48 reg: 49 maxItems: 1 50 51 interrupts: 52 maxItems: 1 53 54 clocks: 55 maxItems: 1 56 57 clock-names: 58 const: dma_clk 59 60required: 61 - compatible 62 - reg 63 - interrupts 64 - clocks 65 - clock-names 66 - "#dma-cells" 67 68unevaluatedProperties: false 69 70examples: 71 - | 72 #include <dt-bindings/clock/at91.h> 73 #include <dt-bindings/dma/at91.h> 74 #include <dt-bindings/interrupt-controller/irq.h> 75 dma-controller@f0008000 { 76 compatible = "atmel,sama5d4-dma"; 77 reg = <0xf0008000 0x1000>; 78 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 79 #dma-cells = <1>; 80 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 81 clock-names = "dma_clk"; 82 }; 83