1*a54ec770SDurai Manickam KR# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*a54ec770SDurai Manickam KR%YAML 1.2 3*a54ec770SDurai Manickam KR--- 4*a54ec770SDurai Manickam KR$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml# 5*a54ec770SDurai Manickam KR$schema: http://devicetree.org/meta-schemas/core.yaml# 6*a54ec770SDurai Manickam KR 7*a54ec770SDurai Manickam KRtitle: Atmel Direct Memory Access Controller (DMA) 8*a54ec770SDurai Manickam KR 9*a54ec770SDurai Manickam KRmaintainers: 10*a54ec770SDurai Manickam KR - Ludovic Desroches <ludovic.desroches@microchip.com> 11*a54ec770SDurai Manickam KR 12*a54ec770SDurai Manickam KRdescription: 13*a54ec770SDurai Manickam KR The Atmel Direct Memory Access Controller (DMAC) transfers data from a source 14*a54ec770SDurai Manickam KR peripheral to a destination peripheral over one or more AMBA buses. One channel 15*a54ec770SDurai Manickam KR is required for each source/destination pair. In the most basic configuration, 16*a54ec770SDurai Manickam KR the DMAC has one master interface and one channel. The master interface reads 17*a54ec770SDurai Manickam KR the data from a source and writes it to a destination. Two AMBA transfers are 18*a54ec770SDurai Manickam KR required for each DMAC data transfer. This is also known as a dual-access transfer. 19*a54ec770SDurai Manickam KR The DMAC is programmed via the APB interface. 20*a54ec770SDurai Manickam KR 21*a54ec770SDurai Manickam KRproperties: 22*a54ec770SDurai Manickam KR compatible: 23*a54ec770SDurai Manickam KR enum: 24*a54ec770SDurai Manickam KR - atmel,at91sam9g45-dma 25*a54ec770SDurai Manickam KR - atmel,at91sam9rl-dma 26*a54ec770SDurai Manickam KR 27*a54ec770SDurai Manickam KR reg: 28*a54ec770SDurai Manickam KR maxItems: 1 29*a54ec770SDurai Manickam KR 30*a54ec770SDurai Manickam KR interrupts: 31*a54ec770SDurai Manickam KR maxItems: 1 32*a54ec770SDurai Manickam KR 33*a54ec770SDurai Manickam KR "#dma-cells": 34*a54ec770SDurai Manickam KR description: 35*a54ec770SDurai Manickam KR Must be <2>, used to represent the number of integer cells in the dma 36*a54ec770SDurai Manickam KR property of client devices. The two cells in order are 37*a54ec770SDurai Manickam KR 1. The first cell represents the channel number. 38*a54ec770SDurai Manickam KR 2. The second cell is 0 for RX and 1 for TX transfers. 39*a54ec770SDurai Manickam KR const: 2 40*a54ec770SDurai Manickam KR 41*a54ec770SDurai Manickam KR clocks: 42*a54ec770SDurai Manickam KR maxItems: 1 43*a54ec770SDurai Manickam KR 44*a54ec770SDurai Manickam KR clock-names: 45*a54ec770SDurai Manickam KR const: dma_clk 46*a54ec770SDurai Manickam KR 47*a54ec770SDurai Manickam KRrequired: 48*a54ec770SDurai Manickam KR - compatible 49*a54ec770SDurai Manickam KR - reg 50*a54ec770SDurai Manickam KR - interrupts 51*a54ec770SDurai Manickam KR - "#dma-cells" 52*a54ec770SDurai Manickam KR - clocks 53*a54ec770SDurai Manickam KR - clock-names 54*a54ec770SDurai Manickam KR 55*a54ec770SDurai Manickam KRadditionalProperties: false 56*a54ec770SDurai Manickam KR 57*a54ec770SDurai Manickam KRexamples: 58*a54ec770SDurai Manickam KR - | 59*a54ec770SDurai Manickam KR dma-controller@ffffec00 { 60*a54ec770SDurai Manickam KR compatible = "atmel,at91sam9g45-dma"; 61*a54ec770SDurai Manickam KR reg = <0xffffec00 0x200>; 62*a54ec770SDurai Manickam KR interrupts = <21>; 63*a54ec770SDurai Manickam KR #dma-cells = <2>; 64*a54ec770SDurai Manickam KR clocks = <&pmc 2 20>; 65*a54ec770SDurai Manickam KR clock-names = "dma_clk"; 66*a54ec770SDurai Manickam KR }; 67*a54ec770SDurai Manickam KR 68*a54ec770SDurai Manickam KR... 69