1*43bcad2bSLars-Peter ClausenAnalog Device AXI-DMAC DMA controller 2*43bcad2bSLars-Peter Clausen 3*43bcad2bSLars-Peter ClausenRequired properties: 4*43bcad2bSLars-Peter Clausen - compatible: Must be "adi,axi-dmac-1.00.a". 5*43bcad2bSLars-Peter Clausen - reg: Specification for the controllers memory mapped register map. 6*43bcad2bSLars-Peter Clausen - interrupts: Specification for the controllers interrupt. 7*43bcad2bSLars-Peter Clausen - clocks: Phandle and specifier to the controllers AXI interface clock 8*43bcad2bSLars-Peter Clausen - #dma-cells: Must be 1. 9*43bcad2bSLars-Peter Clausen 10*43bcad2bSLars-Peter ClausenRequired sub-nodes: 11*43bcad2bSLars-Peter Clausen - adi,channels: This sub-node must contain a sub-node for each DMA channel. For 12*43bcad2bSLars-Peter Clausen the channel sub-nodes the following bindings apply. They must match the 13*43bcad2bSLars-Peter Clausen configuration options of the peripheral as it was instantiated. 14*43bcad2bSLars-Peter Clausen 15*43bcad2bSLars-Peter ClausenRequired properties for adi,channels sub-node: 16*43bcad2bSLars-Peter Clausen - #size-cells: Must be 0 17*43bcad2bSLars-Peter Clausen - #address-cells: Must be 1 18*43bcad2bSLars-Peter Clausen 19*43bcad2bSLars-Peter ClausenRequired channel sub-node properties: 20*43bcad2bSLars-Peter Clausen - reg: Which channel this node refers to. 21*43bcad2bSLars-Peter Clausen - adi,length-width: Width of the DMA transfer length register. 22*43bcad2bSLars-Peter Clausen - adi,source-bus-width, 23*43bcad2bSLars-Peter Clausen adi,destination-bus-width: Width of the source or destination bus in bits. 24*43bcad2bSLars-Peter Clausen - adi,source-bus-type, 25*43bcad2bSLars-Peter Clausen adi,destination-bus-type: Type of the source or destination bus. Must be one 26*43bcad2bSLars-Peter Clausen of the following: 27*43bcad2bSLars-Peter Clausen 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface 28*43bcad2bSLars-Peter Clausen 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface 29*43bcad2bSLars-Peter Clausen 2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface 30*43bcad2bSLars-Peter Clausen 31*43bcad2bSLars-Peter ClausenOptional channel properties: 32*43bcad2bSLars-Peter Clausen - adi,cyclic: Must be set if the channel supports hardware cyclic DMA 33*43bcad2bSLars-Peter Clausen transfers. 34*43bcad2bSLars-Peter Clausen - adi,2d: Must be set if the channel supports hardware 2D DMA transfers. 35*43bcad2bSLars-Peter Clausen 36*43bcad2bSLars-Peter ClausenDMA clients connected to the AXI-DMAC DMA controller must use the format 37*43bcad2bSLars-Peter Clausendescribed in the dma.txt file using a one-cell specifier. The value of the 38*43bcad2bSLars-Peter Clausenspecifier refers to the DMA channel index. 39*43bcad2bSLars-Peter Clausen 40*43bcad2bSLars-Peter ClausenExample: 41*43bcad2bSLars-Peter Clausen 42*43bcad2bSLars-Peter Clausendma: dma@7c420000 { 43*43bcad2bSLars-Peter Clausen compatible = "adi,axi-dmac-1.00.a"; 44*43bcad2bSLars-Peter Clausen reg = <0x7c420000 0x10000>; 45*43bcad2bSLars-Peter Clausen interrupts = <0 57 0>; 46*43bcad2bSLars-Peter Clausen clocks = <&clkc 16>; 47*43bcad2bSLars-Peter Clausen #dma-cells = <1>; 48*43bcad2bSLars-Peter Clausen 49*43bcad2bSLars-Peter Clausen adi,channels { 50*43bcad2bSLars-Peter Clausen #size-cells = <0>; 51*43bcad2bSLars-Peter Clausen #address-cells = <1>; 52*43bcad2bSLars-Peter Clausen 53*43bcad2bSLars-Peter Clausen dma-channel@0 { 54*43bcad2bSLars-Peter Clausen reg = <0>; 55*43bcad2bSLars-Peter Clausen adi,source-bus-width = <32>; 56*43bcad2bSLars-Peter Clausen adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>; 57*43bcad2bSLars-Peter Clausen adi,destination-bus-width = <64>; 58*43bcad2bSLars-Peter Clausen adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>; 59*43bcad2bSLars-Peter Clausen }; 60*43bcad2bSLars-Peter Clausen }; 61*43bcad2bSLars-Peter Clausen}; 62