1e7c7970aSHyun Kwon# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2e7c7970aSHyun Kwon%YAML 1.2 3e7c7970aSHyun Kwon--- 4e7c7970aSHyun Kwon$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml# 5e7c7970aSHyun Kwon$schema: http://devicetree.org/meta-schemas/core.yaml# 6e7c7970aSHyun Kwon 7e7c7970aSHyun Kwontitle: Xilinx ZynqMP DisplayPort Subsystem 8e7c7970aSHyun Kwon 9e7c7970aSHyun Kwondescription: | 10e7c7970aSHyun Kwon The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC) 11e7c7970aSHyun Kwon implements the display and audio pipelines based on the DisplayPort v1.2 12e7c7970aSHyun Kwon standard. The subsystem includes multiple functional blocks as below: 13e7c7970aSHyun Kwon 14e7c7970aSHyun Kwon +------------------------------------------------------------+ 15e7c7970aSHyun Kwon +--------+ | +----------------+ +-----------+ | 16e7c7970aSHyun Kwon | DPDMA | --->| | --> | Video | Video +-------------+ | 17e7c7970aSHyun Kwon | 4x vid | | | | | Rendering | -+--> | | | +------+ 18e7c7970aSHyun Kwon | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 | 19e7c7970aSHyun Kwon +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+ 20e7c7970aSHyun Kwon | | and STC | +-----------+ | | Controller | | +------+ 21e7c7970aSHyun Kwon Live Video --->| | --> | Audio | Audio | |---> | PHY1 | 22e7c7970aSHyun Kwon | | | | Mixer | --+-> | | | +------+ 23e7c7970aSHyun Kwon Live Audio --->| | --> | | || +-------------+ | 24e7c7970aSHyun Kwon | +----------------+ +-----------+ || | 25e7c7970aSHyun Kwon +---------------------------------------||-------------------+ 26e7c7970aSHyun Kwon vv 27e7c7970aSHyun Kwon Blended Video and 28e7c7970aSHyun Kwon Mixed Audio to PL 29e7c7970aSHyun Kwon 30e7c7970aSHyun Kwon The Buffer Manager interacts with external interface such as DMA engines or 31e7c7970aSHyun Kwon live audio/video streams from the programmable logic. The Video Rendering 32e7c7970aSHyun Kwon Pipeline blends the video and graphics layers and performs colorspace 33e7c7970aSHyun Kwon conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort 34e7c7970aSHyun Kwon Source Controller handles the DisplayPort protocol and connects to external 35e7c7970aSHyun Kwon PHYs. 36e7c7970aSHyun Kwon 37e7c7970aSHyun Kwon The subsystem supports 2 video and 2 audio streams, and various pixel formats 38e7c7970aSHyun Kwon and depths up to 4K@30 resolution. 39e7c7970aSHyun Kwon 40e7c7970aSHyun Kwon Please refer to "Zynq UltraScale+ Device Technical Reference Manual" 41e7c7970aSHyun Kwon (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf) 42e7c7970aSHyun Kwon for more details. 43e7c7970aSHyun Kwon 44e7c7970aSHyun Kwonmaintainers: 45e7c7970aSHyun Kwon - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 46e7c7970aSHyun Kwon 47e7c7970aSHyun Kwonproperties: 48e7c7970aSHyun Kwon compatible: 49e7c7970aSHyun Kwon const: xlnx,zynqmp-dpsub-1.7 50e7c7970aSHyun Kwon 51e7c7970aSHyun Kwon reg: 52e7c7970aSHyun Kwon maxItems: 4 53e7c7970aSHyun Kwon reg-names: 54e7c7970aSHyun Kwon items: 55e7c7970aSHyun Kwon - const: dp 56e7c7970aSHyun Kwon - const: blend 57e7c7970aSHyun Kwon - const: av_buf 58e7c7970aSHyun Kwon - const: aud 59e7c7970aSHyun Kwon 60e7c7970aSHyun Kwon interrupts: 61e7c7970aSHyun Kwon maxItems: 1 62e7c7970aSHyun Kwon 63e7c7970aSHyun Kwon clocks: 64e7c7970aSHyun Kwon description: 65e7c7970aSHyun Kwon The APB clock and at least one video clock are mandatory, the audio clock 66e7c7970aSHyun Kwon is optional. 67e7c7970aSHyun Kwon minItems: 2 68e7c7970aSHyun Kwon items: 69e7c7970aSHyun Kwon - description: dp_apb_clk is the APB clock 70e7c7970aSHyun Kwon - description: dp_aud_clk is the Audio clock 71e7c7970aSHyun Kwon - description: 72e7c7970aSHyun Kwon dp_vtc_pixel_clk_in is the non-live video clock (from Processing 73e7c7970aSHyun Kwon System) 74e7c7970aSHyun Kwon - description: 75e7c7970aSHyun Kwon dp_live_video_in_clk is the live video clock (from Programmable 76e7c7970aSHyun Kwon Logic) 77e7c7970aSHyun Kwon clock-names: 78e7c7970aSHyun Kwon oneOf: 79e7c7970aSHyun Kwon - minItems: 2 80e7c7970aSHyun Kwon items: 81e7c7970aSHyun Kwon - const: dp_apb_clk 82e7c7970aSHyun Kwon - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ] 83e7c7970aSHyun Kwon - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ] 84e7c7970aSHyun Kwon - minItems: 3 85e7c7970aSHyun Kwon items: 86e7c7970aSHyun Kwon - const: dp_apb_clk 87e7c7970aSHyun Kwon - const: dp_aud_clk 88e7c7970aSHyun Kwon - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ] 89e7c7970aSHyun Kwon - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ] 90e7c7970aSHyun Kwon 91e7c7970aSHyun Kwon power-domains: 92e7c7970aSHyun Kwon maxItems: 1 93e7c7970aSHyun Kwon 94e7c7970aSHyun Kwon resets: 95e7c7970aSHyun Kwon maxItems: 1 96e7c7970aSHyun Kwon 97e7c7970aSHyun Kwon dmas: 98e7c7970aSHyun Kwon items: 99e7c7970aSHyun Kwon - description: Video layer, plane 0 (RGB or luma) 100e7c7970aSHyun Kwon - description: Video layer, plane 1 (U/V or U) 101e7c7970aSHyun Kwon - description: Video layer, plane 2 (V) 102e7c7970aSHyun Kwon - description: Graphics layer 103e7c7970aSHyun Kwon dma-names: 104e7c7970aSHyun Kwon items: 105e7c7970aSHyun Kwon - const: vid0 106e7c7970aSHyun Kwon - const: vid1 107e7c7970aSHyun Kwon - const: vid2 108e7c7970aSHyun Kwon - const: gfx0 109e7c7970aSHyun Kwon 110e7c7970aSHyun Kwon phys: 111e7c7970aSHyun Kwon description: PHYs for the DP data lanes 112e7c7970aSHyun Kwon minItems: 1 113e7c7970aSHyun Kwon maxItems: 2 114e7c7970aSHyun Kwon phy-names: 115e7c7970aSHyun Kwon minItems: 1 116e7c7970aSHyun Kwon items: 117e7c7970aSHyun Kwon - const: dp-phy0 118e7c7970aSHyun Kwon - const: dp-phy1 119e7c7970aSHyun Kwon 120e7c7970aSHyun Kwonrequired: 121e7c7970aSHyun Kwon - compatible 122e7c7970aSHyun Kwon - reg 123e7c7970aSHyun Kwon - reg-names 124e7c7970aSHyun Kwon - interrupts 125e7c7970aSHyun Kwon - clocks 126e7c7970aSHyun Kwon - clock-names 127e7c7970aSHyun Kwon - power-domains 128e7c7970aSHyun Kwon - resets 129e7c7970aSHyun Kwon - dmas 130e7c7970aSHyun Kwon - dma-names 131e7c7970aSHyun Kwon - phys 132e7c7970aSHyun Kwon - phy-names 133e7c7970aSHyun Kwon 134e7c7970aSHyun KwonadditionalProperties: false 135e7c7970aSHyun Kwon 136e7c7970aSHyun Kwonexamples: 137e7c7970aSHyun Kwon - | 138e7c7970aSHyun Kwon #include <dt-bindings/phy/phy.h> 139e7c7970aSHyun Kwon #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 140e7c7970aSHyun Kwon 141e7c7970aSHyun Kwon display@fd4a0000 { 142e7c7970aSHyun Kwon compatible = "xlnx,zynqmp-dpsub-1.7"; 14364ff609bSRob Herring reg = <0xfd4a0000 0x1000>, 14464ff609bSRob Herring <0xfd4aa000 0x1000>, 14564ff609bSRob Herring <0xfd4ab000 0x1000>, 14664ff609bSRob Herring <0xfd4ac000 0x1000>; 147e7c7970aSHyun Kwon reg-names = "dp", "blend", "av_buf", "aud"; 148e7c7970aSHyun Kwon interrupts = <0 119 4>; 149e7c7970aSHyun Kwon interrupt-parent = <&gic>; 150e7c7970aSHyun Kwon 151e7c7970aSHyun Kwon clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk"; 152e7c7970aSHyun Kwon clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>; 153e7c7970aSHyun Kwon 154e7c7970aSHyun Kwon power-domains = <&pd_dp>; 155e7c7970aSHyun Kwon resets = <&reset ZYNQMP_RESET_DP>; 156e7c7970aSHyun Kwon 157e7c7970aSHyun Kwon dma-names = "vid0", "vid1", "vid2", "gfx0"; 158e7c7970aSHyun Kwon dmas = <&xlnx_dpdma 0>, 159e7c7970aSHyun Kwon <&xlnx_dpdma 1>, 160e7c7970aSHyun Kwon <&xlnx_dpdma 2>, 161e7c7970aSHyun Kwon <&xlnx_dpdma 3>; 162e7c7970aSHyun Kwon 163*5628d9f1SMichal Simek phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 164*5628d9f1SMichal Simek <&psgtr 0 PHY_TYPE_DP 1 3>; 165e7c7970aSHyun Kwon 166e7c7970aSHyun Kwon phy-names = "dp-phy0", "dp-phy1"; 167e7c7970aSHyun Kwon }; 168e7c7970aSHyun Kwon 169e7c7970aSHyun Kwon... 170