xref: /linux/Documentation/devicetree/bindings/display/verisilicon,dc.yaml (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Verisilicon DC-series display controllers
8
9maintainers:
10  - Icenowy Zheng <uwu@icenowy.me>
11
12properties:
13  $nodename:
14    pattern: "^display@[0-9a-f]+$"
15
16  compatible:
17    items:
18      - enum:
19          - thead,th1520-dc8200
20      - const: verisilicon,dc # DC IPs have discoverable ID/revision registers
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  clocks:
29    items:
30      - description: DC Core clock
31      - description: DMA AXI bus clock
32      - description: Configuration AHB bus clock
33      - description: Pixel clock of output 0
34      - description: Pixel clock of output 1
35
36  clock-names:
37    items:
38      - const: core
39      - const: axi
40      - const: ahb
41      - const: pix0
42      - const: pix1
43
44  resets:
45    items:
46      - description: DC Core reset
47      - description: DMA AXI bus reset
48      - description: Configuration AHB bus reset
49
50  reset-names:
51    items:
52      - const: core
53      - const: axi
54      - const: ahb
55
56  ports:
57    $ref: /schemas/graph.yaml#/properties/ports
58
59    properties:
60      port@0:
61        $ref: /schemas/graph.yaml#/properties/port
62        description: The first output channel , endpoint 0 should be
63          used for DPI format output and endpoint 1 should be used
64          for DP format output.
65
66      port@1:
67        $ref: /schemas/graph.yaml#/properties/port
68        description: The second output channel if the DC variant
69          supports. Follow the same endpoint addressing rule with
70          the first port.
71
72required:
73  - compatible
74  - reg
75  - interrupts
76  - clocks
77  - clock-names
78  - ports
79
80additionalProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/interrupt-controller/irq.h>
85    #include <dt-bindings/clock/thead,th1520-clk-ap.h>
86    #include <dt-bindings/reset/thead,th1520-reset.h>
87    soc {
88      #address-cells = <2>;
89      #size-cells = <2>;
90
91      display@ffef600000 {
92        compatible = "thead,th1520-dc8200", "verisilicon,dc";
93        reg = <0xff 0xef600000 0x0 0x100000>;
94        interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
95        clocks = <&clk_vo CLK_DPU_CCLK>,
96                 <&clk_vo CLK_DPU_ACLK>,
97                 <&clk_vo CLK_DPU_HCLK>,
98                 <&clk_vo CLK_DPU_PIXELCLK0>,
99                 <&clk_vo CLK_DPU_PIXELCLK1>;
100        clock-names = "core", "axi", "ahb", "pix0", "pix1";
101        resets = <&rst TH1520_RESET_ID_DPU_CORE>,
102                 <&rst TH1520_RESET_ID_DPU_AXI>,
103                 <&rst TH1520_RESET_ID_DPU_AHB>;
104        reset-names = "core", "axi", "ahb";
105
106        ports {
107          #address-cells = <1>;
108          #size-cells = <0>;
109
110          port@1 {
111            reg = <1>;
112            #address-cells = <1>;
113            #size-cells = <0>;
114
115            dpu_out_dp1: endpoint@1 {
116              reg = <1>;
117              remote-endpoint = <&hdmi_in>;
118            };
119          };
120        };
121      };
122    };
123