1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2# Copyright 2019 Texas Instruments Incorporated 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Texas Instruments AM65x Display Subsystem 9 10maintainers: 11 - Jyri Sarha <jsarha@ti.com> 12 - Tomi Valkeinen <tomi.valkeinen@ti.com> 13 14description: | 15 The AM625 and AM65x TI Keystone Display SubSystem has two output 16 ports and two video planes. In AM65x DSS, the first video port 17 supports 1 OLDI TX and in AM625 DSS, the first video port output is 18 internally routed to 2 OLDI TXes. The second video port supports DPI 19 format. The first plane is full video plane with all features and the 20 second is a "lite plane" without scaling support. 21 The AM62L display subsystem has a single output port which supports DPI 22 format but it only supports single video "lite plane" which does not support 23 scaling. The output port is routed to SoC boundary via DPI interface and same 24 DPI signals are also routed internally to DSI Tx controller present within the 25 SoC. Due to clocking limitations only one of the interface i.e. either DSI or 26 DPI can be used at once. 27 28properties: 29 compatible: 30 enum: 31 - ti,am625-dss 32 - ti,am62a7-dss 33 - ti,am62l-dss 34 - ti,am65x-dss 35 36 reg: 37 description: 38 Addresses to each DSS memory region described in the SoC's TRM. 39 oneOf: 40 - items: 41 - description: common DSS register area 42 - description: VIDL1 light video plane 43 - description: VID video plane 44 - description: OVR1 overlay manager for vp1 45 - description: OVR2 overlay manager for vp2 46 - description: VP1 video port 1 47 - description: VP2 video port 2 48 - description: common1 DSS register area 49 - items: 50 - description: common DSS register area 51 - description: VIDL1 light video plane 52 - description: OVR1 overlay manager for vp1 53 - description: VP1 video port 1 54 - description: common1 DSS register area 55 56 reg-names: 57 oneOf: 58 - items: 59 - const: common 60 - const: vidl1 61 - const: vid 62 - const: ovr1 63 - const: ovr2 64 - const: vp1 65 - const: vp2 66 - const: common1 67 - items: 68 - const: common 69 - const: vidl1 70 - const: ovr1 71 - const: vp1 72 - const: common1 73 74 clocks: 75 minItems: 2 76 items: 77 - description: fck DSS functional clock 78 - description: vp1 Video Port 1 pixel clock 79 - description: vp2 Video Port 2 pixel clock 80 81 clock-names: 82 minItems: 2 83 items: 84 - const: fck 85 - const: vp1 86 - const: vp2 87 88 assigned-clocks: 89 minItems: 1 90 maxItems: 3 91 92 assigned-clock-parents: 93 minItems: 1 94 maxItems: 3 95 96 interrupts: 97 maxItems: 1 98 99 power-domains: 100 maxItems: 1 101 description: phandle to the associated power domain 102 103 dma-coherent: true 104 105 ports: 106 $ref: /schemas/graph.yaml#/properties/ports 107 108 properties: 109 port@0: 110 $ref: /schemas/graph.yaml#/properties/port 111 description: 112 For AM65x DSS, the OLDI output port node from video port 1. 113 For AM625 DSS, the internal DPI output port node from video 114 port 1. 115 For AM62A7 DSS, the port is tied off inside the SoC. 116 For AM62L DSS, the DSS DPI output port node from video port 1 117 or DSI Tx controller node connected to video port 1. 118 properties: 119 endpoint@0: 120 $ref: /schemas/graph.yaml#/properties/endpoint 121 description: 122 For AM625 DSS, VP Connection to OLDI0. 123 For AM65X DSS, OLDI output from the SoC. 124 125 endpoint@1: 126 $ref: /schemas/graph.yaml#/properties/endpoint 127 description: 128 For AM625 DSS, VP Connection to OLDI1. 129 130 anyOf: 131 - required: 132 - endpoint 133 - required: 134 - endpoint@0 135 - endpoint@1 136 137 port@1: 138 $ref: /schemas/graph.yaml#/properties/port 139 description: 140 The DSS DPI output port node from video port 2 141 142 ti,am65x-oldi-io-ctrl: 143 $ref: /schemas/types.yaml#/definitions/phandle 144 description: 145 phandle to syscon device node mapping OLDI IO_CTRL registers. 146 The mapped range should point to OLDI_DAT0_IO_CTRL, map it and 147 following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL, 148 and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI 149 interface to work. 150 151 max-memory-bandwidth: 152 $ref: /schemas/types.yaml#/definitions/uint32 153 description: 154 Input memory (from main memory to dispc) bandwidth limit in 155 bytes per second 156 157 oldi-transmitters: 158 description: 159 Child node under the DSS, to describe all the OLDI transmitters connected 160 to the DSS videoports. 161 type: object 162 additionalProperties: false 163 164 properties: 165 "#address-cells": 166 const: 1 167 168 "#size-cells": 169 const: 0 170 171 patternProperties: 172 '^oldi@[0-1]$': 173 $ref: ti,am625-oldi.yaml# 174 description: OLDI transmitters connected to the DSS VPs 175 176allOf: 177 - if: 178 properties: 179 compatible: 180 contains: 181 const: ti,am62a7-dss 182 then: 183 properties: 184 oldi-transmitters: false 185 ports: 186 properties: 187 port@0: false 188 - if: 189 properties: 190 compatible: 191 contains: 192 const: ti,am62l-dss 193 then: 194 properties: 195 ports: 196 properties: 197 port@1: false 198 reg: 199 maxItems: 5 200 reg-names: 201 maxItems: 5 202 clocks: 203 maxItems: 2 204 clock-names: 205 maxItems: 2 206 else: 207 properties: 208 reg: 209 minItems: 8 210 reg-names: 211 minItems: 8 212 clocks: 213 minItems: 3 214 clock-names: 215 minItems: 3 216 217 - if: 218 properties: 219 compatible: 220 contains: 221 enum: 222 - ti,am62l-dss 223 - ti,am65x-dss 224 then: 225 properties: 226 oldi-transmitters: false 227 ports: 228 properties: 229 port@0: 230 properties: 231 endpoint@1: false 232 233required: 234 - compatible 235 - reg 236 - reg-names 237 - clocks 238 - clock-names 239 - interrupts 240 - ports 241 242additionalProperties: false 243 244examples: 245 - | 246 #include <dt-bindings/interrupt-controller/arm-gic.h> 247 #include <dt-bindings/interrupt-controller/irq.h> 248 #include <dt-bindings/soc/ti,sci_pm_domain.h> 249 250 dss: dss@4a00000 { 251 compatible = "ti,am65x-dss"; 252 reg = <0x04a00000 0x1000>, /* common */ 253 <0x04a02000 0x1000>, /* vidl1 */ 254 <0x04a06000 0x1000>, /* vid */ 255 <0x04a07000 0x1000>, /* ovr1 */ 256 <0x04a08000 0x1000>, /* ovr2 */ 257 <0x04a0a000 0x1000>, /* vp1 */ 258 <0x04a0b000 0x1000>, /* vp2 */ 259 <0x04a01000 0x1000>; /* common1 */ 260 reg-names = "common", "vidl1", "vid", 261 "ovr1", "ovr2", "vp1", "vp2", "common1"; 262 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 263 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 264 clocks = <&k3_clks 67 1>, 265 <&k3_clks 216 1>, 266 <&k3_clks 67 2>; 267 clock-names = "fck", "vp1", "vp2"; 268 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; 269 ports { 270 #address-cells = <1>; 271 #size-cells = <0>; 272 port@0 { 273 reg = <0>; 274 oldi_out0: endpoint { 275 remote-endpoint = <&lcd_in0>; 276 }; 277 }; 278 }; 279 }; 280 281 - | 282 #include <dt-bindings/interrupt-controller/arm-gic.h> 283 #include <dt-bindings/interrupt-controller/irq.h> 284 #include <dt-bindings/soc/ti,sci_pm_domain.h> 285 286 bus { 287 #address-cells = <2>; 288 #size-cells = <2>; 289 dss1: dss@30200000 { 290 compatible = "ti,am625-dss"; 291 reg = <0x00 0x30200000 0x00 0x1000>, /* common */ 292 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ 293 <0x00 0x30206000 0x00 0x1000>, /* vid */ 294 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ 295 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ 296 <0x00 0x3020a000 0x00 0x1000>, /* vp1 */ 297 <0x00 0x3020b000 0x00 0x1000>, /* vp2 */ 298 <0x00 0x30201000 0x00 0x1000>; /* common1 */ 299 reg-names = "common", "vidl1", "vid", 300 "ovr1", "ovr2", "vp1", "vp2", "common1"; 301 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 302 clocks = <&k3_clks 186 6>, 303 <&vp1_clock>, 304 <&k3_clks 186 2>; 305 clock-names = "fck", "vp1", "vp2"; 306 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 307 oldi-transmitters { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 oldi0: oldi@0 { 311 reg = <0>; 312 clocks = <&k3_clks 186 0>; 313 clock-names = "serial"; 314 ti,companion-oldi = <&oldi1>; 315 ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; 316 ports { 317 #address-cells = <1>; 318 #size-cells = <0>; 319 port@0 { 320 reg = <0>; 321 oldi0_in: endpoint { 322 remote-endpoint = <&dpi0_out0>; 323 }; 324 }; 325 port@1 { 326 reg = <1>; 327 oldi0_out: endpoint { 328 remote-endpoint = <&panel_in0>; 329 }; 330 }; 331 }; 332 }; 333 oldi1: oldi@1 { 334 reg = <1>; 335 clocks = <&k3_clks 186 0>; 336 clock-names = "serial"; 337 ti,secondary-oldi; 338 ti,companion-oldi = <&oldi0>; 339 ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; 340 ports { 341 #address-cells = <1>; 342 #size-cells = <0>; 343 port@0 { 344 reg = <0>; 345 oldi1_in: endpoint { 346 remote-endpoint = <&dpi0_out1>; 347 }; 348 }; 349 port@1 { 350 reg = <1>; 351 oldi1_out: endpoint { 352 remote-endpoint = <&panel_in1>; 353 }; 354 }; 355 }; 356 }; 357 }; 358 ports { 359 #address-cells = <1>; 360 #size-cells = <0>; 361 port@0 { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 reg = <0>; 365 dpi0_out0: endpoint@0 { 366 reg = <0>; 367 remote-endpoint = <&oldi0_in>; 368 }; 369 dpi0_out1: endpoint@1 { 370 reg = <1>; 371 remote-endpoint = <&oldi1_in>; 372 }; 373 }; 374 port@1 { 375 reg = <1>; 376 dpi1_out: endpoint { 377 remote-endpoint = <&hdmi_bridge>; 378 }; 379 }; 380 }; 381 }; 382 }; 383