1fe8b45aaSThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2fe8b45aaSThierry Reding%YAML 1.2 3fe8b45aaSThierry Reding--- 4fe8b45aaSThierry Reding$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml# 5fe8b45aaSThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6fe8b45aaSThierry Reding 7fe8b45aaSThierry Redingtitle: NVIDIA Tegra Video Input controller 8fe8b45aaSThierry Reding 9fe8b45aaSThierry Redingmaintainers: 10fe8b45aaSThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11fe8b45aaSThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12fe8b45aaSThierry Reding 13fe8b45aaSThierry Redingproperties: 14fe8b45aaSThierry Reding $nodename: 15fe8b45aaSThierry Reding pattern: "^vi@[0-9a-f]+$" 16fe8b45aaSThierry Reding 17fe8b45aaSThierry Reding compatible: 18fe8b45aaSThierry Reding oneOf: 19fe8b45aaSThierry Reding - const: nvidia,tegra20-vi 20fe8b45aaSThierry Reding - const: nvidia,tegra30-vi 21fe8b45aaSThierry Reding - const: nvidia,tegra114-vi 22fe8b45aaSThierry Reding - const: nvidia,tegra124-vi 23fe8b45aaSThierry Reding - items: 24fe8b45aaSThierry Reding - const: nvidia,tegra132-vi 25fe8b45aaSThierry Reding - const: nvidia,tegra124-vi 26fe8b45aaSThierry Reding - const: nvidia,tegra210-vi 27fe8b45aaSThierry Reding - const: nvidia,tegra186-vi 28fe8b45aaSThierry Reding - const: nvidia,tegra194-vi 29fe8b45aaSThierry Reding 30fe8b45aaSThierry Reding reg: 31fe8b45aaSThierry Reding maxItems: 1 32fe8b45aaSThierry Reding 33fe8b45aaSThierry Reding interrupts: 34fe8b45aaSThierry Reding maxItems: 1 35fe8b45aaSThierry Reding 36fe8b45aaSThierry Reding clocks: 37fe8b45aaSThierry Reding maxItems: 1 38fe8b45aaSThierry Reding 39fe8b45aaSThierry Reding resets: 40fe8b45aaSThierry Reding items: 41fe8b45aaSThierry Reding - description: module reset 42fe8b45aaSThierry Reding 43fe8b45aaSThierry Reding reset-names: 44fe8b45aaSThierry Reding items: 45fe8b45aaSThierry Reding - const: vi 46fe8b45aaSThierry Reding 47fe8b45aaSThierry Reding iommus: 48fe8b45aaSThierry Reding maxItems: 1 49fe8b45aaSThierry Reding 50fe8b45aaSThierry Reding interconnects: 51fe8b45aaSThierry Reding minItems: 4 52fe8b45aaSThierry Reding maxItems: 5 53fe8b45aaSThierry Reding 54fe8b45aaSThierry Reding interconnect-names: 55fe8b45aaSThierry Reding minItems: 4 56fe8b45aaSThierry Reding maxItems: 5 57fe8b45aaSThierry Reding 5821fd06dcSKrzysztof Kozlowski operating-points-v2: true 59fe8b45aaSThierry Reding 60fe8b45aaSThierry Reding power-domains: 61fe8b45aaSThierry Reding items: 62fe8b45aaSThierry Reding - description: phandle to the VENC power domain 63fe8b45aaSThierry Reding 64fe8b45aaSThierry Reding "#address-cells": 65fe8b45aaSThierry Reding const: 1 66fe8b45aaSThierry Reding 67fe8b45aaSThierry Reding "#size-cells": 68fe8b45aaSThierry Reding const: 1 69fe8b45aaSThierry Reding 70fe8b45aaSThierry Reding ranges: 71fe8b45aaSThierry Reding maxItems: 1 72fe8b45aaSThierry Reding 73fe8b45aaSThierry Reding avdd-dsi-csi-supply: 74fe8b45aaSThierry Reding description: DSI/CSI power supply. Must supply 1.2 V. 75fe8b45aaSThierry Reding 76*f17aa778SLuca Ceresoli vip: 77*f17aa778SLuca Ceresoli $ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml 78*f17aa778SLuca Ceresoli 79*f17aa778SLuca Ceresoli ports: 80*f17aa778SLuca Ceresoli $ref: /schemas/graph.yaml#/properties/ports 81*f17aa778SLuca Ceresoli 82*f17aa778SLuca Ceresoli properties: 83*f17aa778SLuca Ceresoli port@0: 84*f17aa778SLuca Ceresoli $ref: /schemas/graph.yaml#/properties/port 85*f17aa778SLuca Ceresoli description: 86*f17aa778SLuca Ceresoli Input from the VIP (parallel input capture) module 87*f17aa778SLuca Ceresoli 88fe8b45aaSThierry RedingpatternProperties: 89fe8b45aaSThierry Reding "^csi@[0-9a-f]+$": 90fe8b45aaSThierry Reding type: object 91fe8b45aaSThierry Reding 92fe8b45aaSThierry RedingadditionalProperties: false 93fe8b45aaSThierry Reding 94fe8b45aaSThierry Redingrequired: 95fe8b45aaSThierry Reding - compatible 96fe8b45aaSThierry Reding - reg 97fe8b45aaSThierry Reding - interrupts 98fe8b45aaSThierry Reding - clocks 99fe8b45aaSThierry Reding 100fe8b45aaSThierry RedingallOf: 101fe8b45aaSThierry Reding - if: 102fe8b45aaSThierry Reding properties: 103fe8b45aaSThierry Reding compatible: 104fe8b45aaSThierry Reding contains: 105fe8b45aaSThierry Reding enum: 106fe8b45aaSThierry Reding - nvidia,tegra20-vi 107fe8b45aaSThierry Reding - nvidia,tegra30-vi 108fe8b45aaSThierry Reding - nvidia,tegra114-vi 109fe8b45aaSThierry Reding - nvidia,tegra124-vi 110fe8b45aaSThierry Reding then: 111fe8b45aaSThierry Reding required: 112fe8b45aaSThierry Reding - resets 113fe8b45aaSThierry Reding - reset-names 114fe8b45aaSThierry Reding else: 115fe8b45aaSThierry Reding required: 116fe8b45aaSThierry Reding - power-domains 117fe8b45aaSThierry Reding 118fe8b45aaSThierry Redingexamples: 119fe8b45aaSThierry Reding - | 120fe8b45aaSThierry Reding #include <dt-bindings/clock/tegra20-car.h> 121fe8b45aaSThierry Reding #include <dt-bindings/interrupt-controller/arm-gic.h> 122fe8b45aaSThierry Reding 123*f17aa778SLuca Ceresoli i2c { 124*f17aa778SLuca Ceresoli #address-cells = <1>; 125*f17aa778SLuca Ceresoli #size-cells = <0>; 126*f17aa778SLuca Ceresoli camera@48 { 127*f17aa778SLuca Ceresoli compatible = "aptina,mt9v111"; 128*f17aa778SLuca Ceresoli reg = <0x48>; 129*f17aa778SLuca Ceresoli clocks = <&camera_clk>; 130*f17aa778SLuca Ceresoli 131*f17aa778SLuca Ceresoli port { 132*f17aa778SLuca Ceresoli mt9v111_out: endpoint { 133*f17aa778SLuca Ceresoli remote-endpoint = <&vi_vip_in>; 134*f17aa778SLuca Ceresoli }; 135*f17aa778SLuca Ceresoli }; 136*f17aa778SLuca Ceresoli }; 137*f17aa778SLuca Ceresoli }; 138*f17aa778SLuca Ceresoli 139fe8b45aaSThierry Reding vi@54080000 { 140fe8b45aaSThierry Reding compatible = "nvidia,tegra20-vi"; 141fe8b45aaSThierry Reding reg = <0x54080000 0x00040000>; 142fe8b45aaSThierry Reding interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_VI>; 144fe8b45aaSThierry Reding resets = <&tegra_car 100>; 145fe8b45aaSThierry Reding reset-names = "vi"; 146*f17aa778SLuca Ceresoli 147*f17aa778SLuca Ceresoli vip { 148*f17aa778SLuca Ceresoli compatible = "nvidia,tegra20-vip"; 149*f17aa778SLuca Ceresoli ports { 150*f17aa778SLuca Ceresoli #address-cells = <1>; 151*f17aa778SLuca Ceresoli #size-cells = <0>; 152*f17aa778SLuca Ceresoli port@0 { 153*f17aa778SLuca Ceresoli reg = <0>; 154*f17aa778SLuca Ceresoli vi_vip_in: endpoint { 155*f17aa778SLuca Ceresoli remote-endpoint = <&mt9v111_out>; 156*f17aa778SLuca Ceresoli }; 157*f17aa778SLuca Ceresoli }; 158*f17aa778SLuca Ceresoli port@1 { 159*f17aa778SLuca Ceresoli reg = <1>; 160*f17aa778SLuca Ceresoli vi_vip_out: endpoint { 161*f17aa778SLuca Ceresoli remote-endpoint = <&vi_in>; 162*f17aa778SLuca Ceresoli }; 163*f17aa778SLuca Ceresoli }; 164*f17aa778SLuca Ceresoli }; 165*f17aa778SLuca Ceresoli }; 166*f17aa778SLuca Ceresoli 167*f17aa778SLuca Ceresoli ports { 168*f17aa778SLuca Ceresoli #address-cells = <1>; 169*f17aa778SLuca Ceresoli #size-cells = <0>; 170*f17aa778SLuca Ceresoli port@0 { 171*f17aa778SLuca Ceresoli reg = <0>; 172*f17aa778SLuca Ceresoli vi_in: endpoint { 173*f17aa778SLuca Ceresoli remote-endpoint = <&vi_vip_out>; 174*f17aa778SLuca Ceresoli }; 175*f17aa778SLuca Ceresoli }; 176*f17aa778SLuca Ceresoli }; 177fe8b45aaSThierry Reding }; 178fe8b45aaSThierry Reding 179fe8b45aaSThierry Reding - | 180fe8b45aaSThierry Reding #include <dt-bindings/clock/tegra210-car.h> 181fe8b45aaSThierry Reding #include <dt-bindings/interrupt-controller/arm-gic.h> 182fe8b45aaSThierry Reding 183fe8b45aaSThierry Reding vi@54080000 { 184fe8b45aaSThierry Reding compatible = "nvidia,tegra210-vi"; 185fe8b45aaSThierry Reding reg = <0x54080000 0x00000700>; 186fe8b45aaSThierry Reding interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 187fe8b45aaSThierry Reding assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 188fe8b45aaSThierry Reding assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 189fe8b45aaSThierry Reding 190fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA210_CLK_VI>; 191fe8b45aaSThierry Reding power-domains = <&pd_venc>; 192fe8b45aaSThierry Reding 193fe8b45aaSThierry Reding #address-cells = <1>; 194fe8b45aaSThierry Reding #size-cells = <1>; 195fe8b45aaSThierry Reding 196fe8b45aaSThierry Reding ranges = <0x0 0x54080000 0x2000>; 197fe8b45aaSThierry Reding 198fe8b45aaSThierry Reding csi@838 { 199fe8b45aaSThierry Reding compatible = "nvidia,tegra210-csi"; 200fe8b45aaSThierry Reding reg = <0x838 0x1300>; 201fe8b45aaSThierry Reding assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 202fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CILCD>, 203fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CILE>, 204fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CSI_TPG>; 205fe8b45aaSThierry Reding assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 206fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_PLL_P>, 207fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_PLL_P>; 208fe8b45aaSThierry Reding assigned-clock-rates = <102000000>, 209fe8b45aaSThierry Reding <102000000>, 210fe8b45aaSThierry Reding <102000000>, 211fe8b45aaSThierry Reding <972000000>; 212fe8b45aaSThierry Reding 213fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA210_CLK_CSI>, 214fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CILAB>, 215fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CILCD>, 216fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CILE>, 217fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CSI_TPG>; 218fe8b45aaSThierry Reding clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 219fe8b45aaSThierry Reding power-domains = <&pd_sor>; 220fe8b45aaSThierry Reding }; 221fe8b45aaSThierry Reding }; 222