xref: /linux/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml (revision 34dc1baba215b826e454b8d19e4f24adbeb7d00d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-tvo.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra TV Encoder Output
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  $nodename:
15    pattern: "^tvo@[0-9a-f]+$"
16
17  compatible:
18    enum:
19      - nvidia,tegra20-tvo
20      - nvidia,tegra30-tvo
21      - nvidia,tegra114-tvo
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    items:
31      - description: module clock
32
33  operating-points-v2: true
34
35  power-domains:
36    items:
37      - description: phandle to the core power domain
38
39additionalProperties: false
40
41required:
42  - compatible
43  - reg
44  - interrupts
45  - clocks
46
47examples:
48  - |
49    #include <dt-bindings/clock/tegra20-car.h>
50    #include <dt-bindings/interrupt-controller/arm-gic.h>
51
52    tvo@542c0000 {
53        compatible = "nvidia,tegra20-tvo";
54        reg = <0x542c0000 0x00040000>;
55        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
56        clocks = <&tegra_car TEGRA20_CLK_TVO>;
57    };
58