xref: /linux/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml (revision ae22a94997b8a03dcb3c922857c203246711f9d4) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra Video Encoder
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  $nodename:
15    pattern: "^mpe@[0-9a-f]+$"
16
17  compatible:
18    enum:
19      - nvidia,tegra20-mpe
20      - nvidia,tegra30-mpe
21      - nvidia,tegra114-mpe
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    items:
31      - description: module clock
32
33  resets:
34    items:
35      - description: module reset
36
37  reset-names:
38    items:
39      - const: mpe
40
41  iommus:
42    maxItems: 1
43
44  interconnects:
45    maxItems: 6
46
47  interconnect-names:
48    maxItems: 6
49
50  operating-points-v2: true
51
52  power-domains:
53    items:
54      - description: phandle to the MPE power domain
55
56additionalProperties: false
57
58examples:
59  - |
60    #include <dt-bindings/clock/tegra20-car.h>
61    #include <dt-bindings/interrupt-controller/arm-gic.h>
62
63    mpe@54040000 {
64        compatible = "nvidia,tegra20-mpe";
65        reg = <0x54040000 0x00040000>;
66        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
67        clocks = <&tegra_car TEGRA20_CLK_MPE>;
68        resets = <&tegra_car 60>;
69        reset-names = "mpe";
70    };
71