xref: /linux/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml (revision 4359a011e259a4608afc7fb3635370c9d4ba5943) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra Video Encoder
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  $nodename:
15    pattern: "^mpe@[0-9a-f]+$"
16
17  compatible:
18    enum:
19      - nvidia,tegra20-mpe
20      - nvidia,tegra30-mpe
21      - nvidia,tegra114-mpe
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    items:
31      - description: module clock
32
33  resets:
34    items:
35      - description: module reset
36
37  reset-names:
38    items:
39      - const: mpe
40
41  iommus:
42    maxItems: 1
43
44  interconnects:
45    minItems: 6
46    maxItems: 6
47
48  interconnect-names:
49    minItems: 6
50    maxItems: 6
51
52  operating-points-v2:
53    $ref: "/schemas/types.yaml#/definitions/phandle"
54
55  power-domains:
56    items:
57      - description: phandle to the MPE power domain
58
59additionalProperties: false
60
61examples:
62  - |
63    #include <dt-bindings/clock/tegra20-car.h>
64    #include <dt-bindings/interrupt-controller/arm-gic.h>
65
66    mpe@54040000 {
67        compatible = "nvidia,tegra20-mpe";
68        reg = <0x54040000 0x00040000>;
69        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
70        clocks = <&tegra_car TEGRA20_CLK_MPE>;
71        resets = <&tegra_car 60>;
72        reset-names = "mpe";
73    };
74