1fe8b45aaSThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2fe8b45aaSThierry Reding%YAML 1.2 3fe8b45aaSThierry Reding--- 4fe8b45aaSThierry Reding$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml# 5fe8b45aaSThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6fe8b45aaSThierry Reding 7fe8b45aaSThierry Redingtitle: NVIDIA Tegra Video Encoder 8fe8b45aaSThierry Reding 9fe8b45aaSThierry Redingmaintainers: 10fe8b45aaSThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11fe8b45aaSThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12fe8b45aaSThierry Reding 13fe8b45aaSThierry Redingproperties: 14fe8b45aaSThierry Reding $nodename: 15fe8b45aaSThierry Reding pattern: "^mpe@[0-9a-f]+$" 16fe8b45aaSThierry Reding 17fe8b45aaSThierry Reding compatible: 18fe8b45aaSThierry Reding enum: 19fe8b45aaSThierry Reding - nvidia,tegra20-mpe 20fe8b45aaSThierry Reding - nvidia,tegra30-mpe 21fe8b45aaSThierry Reding - nvidia,tegra114-mpe 22fe8b45aaSThierry Reding 23fe8b45aaSThierry Reding reg: 24fe8b45aaSThierry Reding maxItems: 1 25fe8b45aaSThierry Reding 26fe8b45aaSThierry Reding interrupts: 27fe8b45aaSThierry Reding maxItems: 1 28fe8b45aaSThierry Reding 29fe8b45aaSThierry Reding clocks: 30fe8b45aaSThierry Reding items: 31fe8b45aaSThierry Reding - description: module clock 32fe8b45aaSThierry Reding 33fe8b45aaSThierry Reding resets: 34fe8b45aaSThierry Reding items: 35fe8b45aaSThierry Reding - description: module reset 36fe8b45aaSThierry Reding 37fe8b45aaSThierry Reding reset-names: 38fe8b45aaSThierry Reding items: 39fe8b45aaSThierry Reding - const: mpe 40fe8b45aaSThierry Reding 41fe8b45aaSThierry Reding iommus: 42fe8b45aaSThierry Reding maxItems: 1 43fe8b45aaSThierry Reding 44fe8b45aaSThierry Reding interconnects: 45fe8b45aaSThierry Reding maxItems: 6 46fe8b45aaSThierry Reding 47fe8b45aaSThierry Reding interconnect-names: 48fe8b45aaSThierry Reding maxItems: 6 49fe8b45aaSThierry Reding 50*21fd06dcSKrzysztof Kozlowski operating-points-v2: true 51fe8b45aaSThierry Reding 52fe8b45aaSThierry Reding power-domains: 53fe8b45aaSThierry Reding items: 54fe8b45aaSThierry Reding - description: phandle to the MPE power domain 55fe8b45aaSThierry Reding 56fe8b45aaSThierry RedingadditionalProperties: false 57fe8b45aaSThierry Reding 58fe8b45aaSThierry Redingexamples: 59fe8b45aaSThierry Reding - | 60fe8b45aaSThierry Reding #include <dt-bindings/clock/tegra20-car.h> 61fe8b45aaSThierry Reding #include <dt-bindings/interrupt-controller/arm-gic.h> 62fe8b45aaSThierry Reding 63fe8b45aaSThierry Reding mpe@54040000 { 64fe8b45aaSThierry Reding compatible = "nvidia,tegra20-mpe"; 65fe8b45aaSThierry Reding reg = <0x54040000 0x00040000>; 66fe8b45aaSThierry Reding interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 67fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_MPE>; 68fe8b45aaSThierry Reding resets = <&tegra_car 60>; 69fe8b45aaSThierry Reding reset-names = "mpe"; 70fe8b45aaSThierry Reding }; 71