xref: /linux/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml (revision d30c1683aaecb93d2ab95685dc4300a33d3cea7a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra ISP processor
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  compatible:
15    oneOf:
16      - enum:
17          - nvidia,tegra20-isp
18          - nvidia,tegra30-isp
19          - nvidia,tegra114-isp
20          - nvidia,tegra124-isp
21          - nvidia,tegra210-isp
22
23      - items:
24          - const: nvidia,tegra132-isp
25          - const: nvidia,tegra124-isp
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    items:
35      - description: module clock
36
37  resets:
38    items:
39      - description: module reset
40
41  reset-names:
42    items:
43      - const: isp
44
45  iommus:
46    maxItems: 1
47
48  interconnects:
49    items:
50      - description: memory write client
51
52  interconnect-names:
53    items:
54      - const: dma-mem # write
55
56  power-domains:
57    items:
58      - description: phandle to the VENC or core power domain
59
60additionalProperties: false
61
62examples:
63  - |
64    #include <dt-bindings/clock/tegra20-car.h>
65    #include <dt-bindings/interrupt-controller/arm-gic.h>
66
67    isp@54100000 {
68        compatible = "nvidia,tegra20-isp";
69        reg = <0x54100000 0x00040000>;
70        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
71        clocks = <&tegra_car TEGRA20_CLK_ISP>;
72        resets = <&tegra_car 23>;
73        reset-names = "isp";
74    };
75