xref: /linux/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra host1x controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13description: The host1x top-level node defines a number of children, each
14  representing one of the host1x client modules defined in this binding.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - nvidia,tegra20-host1x
21          - nvidia,tegra30-host1x
22          - nvidia,tegra114-host1x
23          - nvidia,tegra124-host1x
24          - nvidia,tegra210-host1x
25          - nvidia,tegra186-host1x
26          - nvidia,tegra194-host1x
27          - nvidia,tegra234-host1x
28
29      - items:
30          - const: nvidia,tegra132-host1x
31          - const: nvidia,tegra124-host1x
32
33  reg:
34    minItems: 1
35    maxItems: 3
36
37  reg-names:
38    minItems: 1
39    maxItems: 3
40
41  interrupts:
42    minItems: 1
43    maxItems: 9
44
45  interrupt-names:
46    minItems: 1
47    maxItems: 9
48
49  '#address-cells':
50    description: The number of cells used to represent physical base addresses
51      in the host1x address space.
52    enum: [1, 2]
53
54  '#size-cells':
55    description: The number of cells used to represent the size of an address
56      range in the host1x address space.
57    enum: [1, 2]
58
59  ranges:
60    maxItems: 1
61
62  clocks:
63    description: Must contain one entry, for the module clock. See
64      ../clocks/clock-bindings.txt for details.
65
66  clock-names:
67    items:
68      - const: host1x
69
70  resets:
71    minItems: 1 # MC reset is optional on Tegra186 and later
72    items:
73      - description: module reset
74      - description: memory client hotflush reset
75
76  reset-names:
77    minItems: 1 # MC reset is optional on Tegra186 and later
78    items:
79      - const: host1x
80      - const: mc
81
82  iommus:
83    maxItems: 1
84
85  interconnects:
86    items:
87      - description: memory read client for host1x
88
89  interconnect-names:
90    items:
91      - const: dma-mem # read
92
93  operating-points-v2: true
94
95  power-domains:
96    items:
97      - description: phandle to the HEG or core power domain
98
99required:
100  - compatible
101  - interrupts
102  - interrupt-names
103  - '#address-cells'
104  - '#size-cells'
105  - ranges
106  - reg
107  - clocks
108  - clock-names
109
110unevaluatedProperties:
111  type: object
112
113allOf:
114  - if:
115      properties:
116        compatible:
117          contains:
118            enum:
119              - nvidia,tegra20-host1x
120              - nvidia,tegra30-host1x
121              - nvidia,tegra114-host1x
122              - nvidia,tegra124-host1x
123              - nvidia,tegra210-host1x
124    then:
125      properties:
126        interrupts:
127          items:
128            - description: host1x syncpoint interrupt
129            - description: host1x general interrupt
130
131        interrupt-names:
132          items:
133            - const: syncpt
134            - const: host1x
135      required:
136        - resets
137        - reset-names
138  - if:
139      properties:
140        compatible:
141          contains:
142            enum:
143              - nvidia,tegra186-host1x
144              - nvidia,tegra194-host1x
145    then:
146      properties:
147        reg-names:
148          items:
149            - const: hypervisor
150            - const: vm
151
152        reg:
153          items:
154            - description: region used by the hypervisor
155            - description: region assigned to the virtual machine
156
157        resets:
158          maxItems: 1
159
160        reset-names:
161          maxItems: 1
162
163        interrupts:
164          items:
165            - description: host1x syncpoint interrupt
166            - description: host1x general interrupt
167
168        interrupt-names:
169          items:
170            - const: syncpt
171            - const: host1x
172
173        iommu-map:
174          description: Specification of stream IDs available for memory context device
175            use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
176            usable stream IDs.
177
178      required:
179        - reg-names
180  - if:
181      properties:
182        compatible:
183          contains:
184            enum:
185              - nvidia,tegra194-host1x
186    then:
187      properties:
188        dma-coherent: true
189  - if:
190      properties:
191        compatible:
192          contains:
193            enum:
194              - nvidia,tegra234-host1x
195    then:
196      properties:
197        reg-names:
198          items:
199            - const: common
200            - const: hypervisor
201            - const: vm
202
203        reg:
204          items:
205            - description: region used by host1x server
206            - description: region used by the hypervisor
207            - description: region assigned to the virtual machine
208
209        interrupts:
210          items:
211            - description: host1x syncpoint interrupt 0
212            - description: host1x syncpoint interrupt 1
213            - description: host1x syncpoint interrupt 2
214            - description: host1x syncpoint interrupt 3
215            - description: host1x syncpoint interrupt 4
216            - description: host1x syncpoint interrupt 5
217            - description: host1x syncpoint interrupt 6
218            - description: host1x syncpoint interrupt 7
219            - description: host1x general interrupt
220
221        interrupt-names:
222          items:
223            - const: syncpt0
224            - const: syncpt1
225            - const: syncpt2
226            - const: syncpt3
227            - const: syncpt4
228            - const: syncpt5
229            - const: syncpt6
230            - const: syncpt7
231            - const: host1x
232
233        iommu-map:
234          description: Specification of stream IDs available for memory context device
235            use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
236            usable stream IDs.
237
238        dma-coherent: true
239
240      required:
241        - reg-names
242
243examples:
244  - |
245    #include <dt-bindings/clock/tegra20-car.h>
246    #include <dt-bindings/gpio/tegra-gpio.h>
247    #include <dt-bindings/memory/tegra20-mc.h>
248
249    host1x@50000000 {
250        compatible = "nvidia,tegra20-host1x";
251        reg = <0x50000000 0x00024000>;
252        interrupts = <0 65 0x04>, /* mpcore syncpt */
253                     <0 67 0x04>; /* mpcore general */
254        interrupt-names = "syncpt", "host1x";
255        clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
256        clock-names = "host1x";
257        resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
258        reset-names = "host1x", "mc";
259
260        #address-cells = <1>;
261        #size-cells = <1>;
262
263        ranges = <0x54000000 0x54000000 0x04000000>;
264
265        mpe@54040000 {
266            compatible = "nvidia,tegra20-mpe";
267            reg = <0x54040000 0x00040000>;
268            interrupts = <0 68 0x04>;
269            clocks = <&tegra_car TEGRA20_CLK_MPE>;
270            resets = <&tegra_car 60>;
271            reset-names = "mpe";
272        };
273
274        vi@54080000 {
275            compatible = "nvidia,tegra20-vi";
276            reg = <0x54080000 0x00040000>;
277            interrupts = <0 69 0x04>;
278            clocks = <&tegra_car TEGRA20_CLK_VI>;
279            resets = <&tegra_car 100>;
280            reset-names = "vi";
281        };
282
283        epp@540c0000 {
284            compatible = "nvidia,tegra20-epp";
285            reg = <0x540c0000 0x00040000>;
286            interrupts = <0 70 0x04>;
287            clocks = <&tegra_car TEGRA20_CLK_EPP>;
288            resets = <&tegra_car 19>;
289            reset-names = "epp";
290        };
291
292        isp@54100000 {
293            compatible = "nvidia,tegra20-isp";
294            reg = <0x54100000 0x00040000>;
295            interrupts = <0 71 0x04>;
296            clocks = <&tegra_car TEGRA20_CLK_ISP>;
297            resets = <&tegra_car 23>;
298            reset-names = "isp";
299        };
300
301        gr2d@54140000 {
302            compatible = "nvidia,tegra20-gr2d";
303            reg = <0x54140000 0x00040000>;
304            interrupts = <0 72 0x04>;
305            clocks = <&tegra_car TEGRA20_CLK_GR2D>;
306            resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
307            reset-names = "2d", "mc";
308        };
309
310        gr3d@54180000 {
311            compatible = "nvidia,tegra20-gr3d";
312            reg = <0x54180000 0x00040000>;
313            clocks = <&tegra_car TEGRA20_CLK_GR3D>;
314            resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
315            reset-names = "3d", "mc";
316        };
317
318        dc@54200000 {
319            compatible = "nvidia,tegra20-dc";
320            reg = <0x54200000 0x00040000>;
321            interrupts = <0 73 0x04>;
322            clocks = <&tegra_car TEGRA20_CLK_DISP1>;
323            clock-names = "dc";
324            resets = <&tegra_car 27>;
325            reset-names = "dc";
326
327            rgb {
328            };
329        };
330
331        dc@54240000 {
332            compatible = "nvidia,tegra20-dc";
333            reg = <0x54240000 0x00040000>;
334            interrupts = <0 74 0x04>;
335            clocks = <&tegra_car TEGRA20_CLK_DISP2>;
336            clock-names = "dc";
337            resets = <&tegra_car 26>;
338            reset-names = "dc";
339
340            rgb {
341            };
342        };
343
344        hdmi@54280000 {
345            compatible = "nvidia,tegra20-hdmi";
346            reg = <0x54280000 0x00040000>;
347            interrupts = <0 75 0x04>;
348            clocks = <&tegra_car TEGRA20_CLK_HDMI>,
349                     <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
350            clock-names = "hdmi", "parent";
351            resets = <&tegra_car 51>;
352            reset-names = "hdmi";
353
354            hdmi-supply = <&vdd_5v0_hdmi>;
355            pll-supply = <&vdd_hdmi_pll>;
356            vdd-supply = <&vdd_3v3_hdmi>;
357
358            nvidia,ddc-i2c-bus = <&hdmi_ddc>;
359            nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
360        };
361
362        tvo@542c0000 {
363            compatible = "nvidia,tegra20-tvo";
364            reg = <0x542c0000 0x00040000>;
365            interrupts = <0 76 0x04>;
366            clocks = <&tegra_car TEGRA20_CLK_TVO>;
367        };
368
369        dsi@54300000 {
370            compatible = "nvidia,tegra20-dsi";
371            reg = <0x54300000 0x00040000>;
372            clocks = <&tegra_car TEGRA20_CLK_DSI>,
373                     <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
374            clock-names = "dsi", "parent";
375            resets = <&tegra_car 48>;
376            reset-names = "dsi";
377        };
378    };
379
380  - |
381    #include <dt-bindings/clock/tegra210-car.h>
382    #include <dt-bindings/interrupt-controller/arm-gic.h>
383    #include <dt-bindings/memory/tegra210-mc.h>
384
385    host1x@50000000 {
386        compatible = "nvidia,tegra210-host1x";
387        reg = <0x50000000 0x00024000>;
388        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
389                     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
390        interrupt-names = "syncpt", "host1x";
391        clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
392        clock-names = "host1x";
393        resets = <&tegra_car 28>;
394        reset-names = "host1x";
395
396        #address-cells = <1>;
397        #size-cells = <1>;
398
399        ranges = <0x54000000 0x54000000 0x01000000>;
400        iommus = <&mc TEGRA_SWGROUP_HC>;
401
402        vi@54080000 {
403            compatible = "nvidia,tegra210-vi";
404            reg = <0x54080000 0x00000700>;
405            interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
406            assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
407            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
408
409            clocks = <&tegra_car TEGRA210_CLK_VI>;
410            power-domains = <&pd_venc>;
411
412            #address-cells = <1>;
413            #size-cells = <1>;
414
415            ranges = <0x0 0x54080000 0x2000>;
416
417            csi@838 {
418                compatible = "nvidia,tegra210-csi";
419                reg = <0x838 0x1300>;
420                assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
421                                  <&tegra_car TEGRA210_CLK_CILCD>,
422                                  <&tegra_car TEGRA210_CLK_CILE>,
423                                  <&tegra_car TEGRA210_CLK_CSI_TPG>;
424                assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
425                                         <&tegra_car TEGRA210_CLK_PLL_P>,
426                                         <&tegra_car TEGRA210_CLK_PLL_P>;
427                assigned-clock-rates = <102000000>,
428                                       <102000000>,
429                                       <102000000>,
430                                       <972000000>;
431
432                clocks = <&tegra_car TEGRA210_CLK_CSI>,
433                         <&tegra_car TEGRA210_CLK_CILAB>,
434                         <&tegra_car TEGRA210_CLK_CILCD>,
435                         <&tegra_car TEGRA210_CLK_CILE>,
436                         <&tegra_car TEGRA210_CLK_CSI_TPG>;
437                clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
438                power-domains = <&pd_sor>;
439            };
440        };
441    };
442