xref: /linux/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml (revision c31f4aa8fed048fa70e742c4bb49bb48dc489ab3) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra Encoder Pre-Processor
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  $nodename:
15    pattern: "^epp@[0-9a-f]+$"
16
17  compatible:
18    oneOf:
19      - enum:
20          - nvidia,tegra20-epp
21          - nvidia,tegra30-epp
22          - nvidia,tegra114-epp
23          - nvidia,tegra124-epp
24
25      - items:
26          - const: nvidia,tegra132-epp
27          - const: nvidia,tegra124-epp
28
29  reg:
30    maxItems: 1
31
32  interrupts:
33    maxItems: 1
34
35  clocks:
36    maxItems: 1
37
38  resets:
39    items:
40      - description: module reset
41
42  reset-names:
43    items:
44      - const: epp
45
46  iommus:
47    maxItems: 1
48
49  interconnects:
50    maxItems: 4
51
52  interconnect-names:
53    maxItems: 4
54
55  operating-points-v2: true
56
57  power-domains:
58    items:
59      - description: phandle to the core power domain
60
61additionalProperties: false
62
63examples:
64  - |
65    #include <dt-bindings/clock/tegra20-car.h>
66    #include <dt-bindings/interrupt-controller/arm-gic.h>
67
68    epp@540c0000 {
69        compatible = "nvidia,tegra20-epp";
70        reg = <0x540c0000 0x00040000>;
71        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
72        clocks = <&tegra_car TEGRA20_CLK_EPP>;
73        resets = <&tegra_car 19>;
74        reset-names = "epp";
75    };
76